Verilog Task

A function is meant to do some processing on the input and return a single value, whereas a task is more general and can calculate multiple result values and return them using output and inout type arguments. Tasks can contain simulation time consuming elements such as @, posedge and others. There are two ways in which tasks can be written, which we'll see next.

Syntax

 
  // Style 1
  task [name];
    input  [port_list];
    inout  [port_list];
    output [port_list];
    begin
      [statements]
    end
  endtask
 
  // Style 2
  task [name] (input [port_list], inout [port_list], output [port_list]);
    begin
      [statements]
    end
  endtask
 

The keyword automatic will make the task reentrant, otherwise it will be static by default. If a task is static, then all its member variables will be shared across different invocations of the same task that has been launched to run concurrently. Note that auomatic task items cannot be accessed by hierarchical references.

Calling a task

If the task does not need any arguments, then a list of arguments can be avoided. If the task needs arguments, they can be provided in the same statement as its invocation.

 
  task sum (input [7:0] a, b, output [7:0] c);
    begin
      c = a + b;
    end
  endtask
// or   
  task sum;
    input  [7:0] a, b;
    output [7:0] c;
    begin
      c = a + b;
    end
  endtask
 
 
  initial begin
    reg [7:0] x, y , z;
    sum (x, y, z);          
  end
 

The task-enabling arguments (x, y, z) correspond to the arguments (a, b, c) defined by the task. Since a and b are inputs, values of x and y will be placed in a and b respectively. Because c is declared as an output and connected with z during invocation, the sum will automatically be passed to the variable z from c.

Difference between function and task