Data that cannot be processed is quite useless, there'll always be some form calculation required in digital circuits and computer systems. Let's look at some of the operators in Verilog that would enable synthesis tools realize appropriate hardware elements.

## Verilog Arithmetic Operators

If the second operand of a division or modulus operator is zero, then the result will be X. If either operand of the power operator is real, then the result will also be real. The result will be 1 if the second operand of a power operator is 0 (a0).

Operator Description
a + b a plus b
a - b a minus b
a * b a multiplied by b
a / b a divided by b
a % b a modulo b
a ** b a to the power of b

An example of how arithmetic operators are used is given below.

```  ```

module des;
reg [7:0]  data1;
reg [7:0]  data2;

initial begin
data1 = 45;
data2 = 9;

\$display ("Add + = %d", data1 + data2);
\$display ("Sub - = %d", data1 - data2);
\$display ("Mul * = %d", data1 * data2);
\$display ("Div / = %d", data1 / data2);
\$display ("Mod %% = %d", data1 % data2);
\$display ("Pow ** = %d", data2 ** 2);

end
endmodule

```
```
Simulation Log
```ncsim> run
Sub - =  36
Mul * = 149
Div / =   5
Mod % =   0
Pow ** =  81
ncsim: *W,RNQUIE: Simulation is complete.

```

## Verilog Relational Operators

An expression with the relational operator will result in a 1 if the expression is evaluated to be true, and 0 if it is false. If either of the operands is X or Z, then the result will be X. Relational operators have a lower precedence than arithmetic operators and all relational operators have the same precedence.

Operator Description
a < b a less than b
a > b a greater than b
a <= b a less than or equal to b
a >= b a greater than or equal to b
```  ```

module des;
reg [7:0]  data1;
reg [7:0]  data2;

initial begin
data1 = 45;
data2 = 9;
\$display ("Result for data1 >= data2 : %0d", data1 >= data2);

data1 = 45;
data2 = 45;
\$display ("Result for data1 <= data2 : %0d", data1 <= data2); data1 = 9; data2 = 8; \$display ("Result for data1 > data2 : %0d", data1 > data2);

data1 = 22;
data2 = 22;
\$display ("Result for data1 < data2 : %0d", data1 < data2);

end
endmodule

```
```
Simulation Log
```ncsim> run
Result for data1 >= data2 : 1
Result for data1 <= data2 : 1
Result for data1 > data2 : 1
Result for data1 < data2 : 0
ncsim: *W,RNQUIE: Simulation is complete.

```

## Verilog Equality Operators

Equality operators have the same precedence amongst them and are lower in precedence than relational operators. The result is 1 if true, and 0 if false. If either of the operands of logical-equality (==) or logical-inequality (!=) is X or Z, then the result will be X. You may use case-equality operator (===) or case-inequality operator (!==) to match including X and Z and will always have a known value.

Operator Description
a === b a equal to b, including x and z
a !== b a not equal to b, including x and z
a == b a equal to b, result can be unknown
a != b a not equal to b, result can be unknown
```  ```

module des;
reg [7:0]  data1;
reg [7:0]  data2;

initial begin
data1 = 45;     data2 = 9;      \$display ("Result for data1(%0d) === data2(%0d) : %0d", data1, data2, data1 === data2);
data1 = 'b101x; data2 = 'b1011; \$display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2);
data1 = 'b101x; data2 = 'b101x; \$display ("Result for data1(%0b) === data2(%0b) : %0d", data1, data2, data1 === data2);
data1 = 'b101z; data2 = 'b1z00; \$display ("Result for data1(%0b) !== data2(%0b) : %0d", data1, data2, data1 !== data2);
data1 = 39;     data2 = 39;     \$display ("Result for data1(%0d) == data2(%0d) : %0d", data1, data2, data1 == data2);
data1 = 14;     data2 = 14;     \$display ("Result for data1(%0d) != data2(%0d) : %0d", data1, data2, data1 != data2);
end
endmodule

```
```
Simulation Log
```ncsim> run
Result for data1(45) === data2(9) : 0
Result for data1(101x) === data2(1011) : 0
Result for data1(101x) === data2(101x) : 1
Result for data1(101z) !== data2(1z00) : 1
Result for data1(39) == data2(39) : 1
Result for data1(14) != data2(14) : 0
ncsim: *W,RNQUIE: Simulation is complete.

```

## Verilog Logical Operators

The result of a logical and (&&) is 1 or true when both its operands are true or non-zero. The result of a logical or (||) is 1 or true when either of its operands are true or non-zero. If either of the operands is X, then the result will be X as well. The logical negation (!) operator will convert a non-zero or true operand into 0 and a zero or false operand into 1, while an X will remain as an X.

Operator Description
a && b evaluates to true if a and b are true
a || b evaluates to true if a or b are true
!a Converts non-zero value to zero, and vice versa
```  ```

module des;
reg [7:0]  data1;
reg [7:0]  data2;

initial begin
data1 = 45;     data2 = 9; \$display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
data1 = 0;      data2 = 4; \$display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
data1 = 'dx;    data2 = 3; \$display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
data1 = 'b101z; data2 = 5; \$display ("Result of data1(%0d) && data2(%0d) : %0d", data1, data2, data1 && data2);
data1 = 45;     data2 = 9; \$display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
data1 = 0;      data2 = 4; \$display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
data1 = 'dx;    data2 = 3; \$display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
data1 = 'b101z; data2 = 5; \$display ("Result of data1(%0d) || data2(%0d) : %0d", data1, data2, data1 || data2);
data1 = 4;                 \$display ("Result of !data1(%0d) : %0d", data1, !data1);
data1 = 0;                 \$display ("Result of !data1(%0d) : %0d", data1, !data1);
end
endmodule

```
```
Simulation Log
```ncsim> run
Result of data1(45) && data2(9) : 1
Result of data1(0) && data2(4) : 0
Result of data1(x) && data2(3) : x
Result of data1(Z) && data2(5) : 1
Result of data1(45) || data2(9) : 1
Result of data1(0) || data2(4) : 1
Result of data1(x) || data2(3) : 1
Result of data1(Z) || data2(5) : 1
Result of !data1(4) : 0
Result of !data1(0) : 1
ncsim: *W,RNQUIE: Simulation is complete.

```

## Verilog Bitwise Operators

This operator will combine a bit in one operand with its corresponding bit in the other operand to calculate a single bit result.

& 0 1 x z
0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
| 0 1 x z
0 0 1 x x
1 1 1 1 1
x x 1 x x
z x 1 x x
```  ```

module des;
reg 		 data1  ;
reg 		 data2  ;
int 		 i, j;

initial begin
data1 = 0;  data2 = 0;
data1 = 1;  data2 = 1;
data1 = 'x; data2 = 'x;
data1 = 'z; data2 = 'z;

for (i = 0; i < 4; i += 1) begin
for (j = 0; j < 4; j += 1) begin
\$display ("data1(%0d) & data2(%0d) = %0d", data1[i], data2[j], data1[i] & data2[j]);
end
end
end
endmodule

```
```
Simulation Log
```ncsim> run
data1(0) & data2(0) = 0
data1(0) & data2(1) = 0
data1(0) & data2(x) = 0
data1(0) & data2(z) = 0
data1(1) & data2(0) = 0
data1(1) & data2(1) = 1
data1(1) & data2(x) = x
data1(1) & data2(z) = x
data1(x) & data2(0) = 0
data1(x) & data2(1) = x
data1(x) & data2(x) = x
data1(x) & data2(z) = x
data1(z) & data2(0) = 0
data1(z) & data2(1) = x
data1(z) & data2(x) = x
data1(z) & data2(z) = x
ncsim: *W,RNQUIE: Simulation is complete.

```

## Verilog Shift Operators

There are two kinds of shift operators:

• Logical shift operators     : <<  and >>
• Arithmetic shift operators : <<< and >>>

```  ```

module des;
reg [7:0] data;
int       i;

initial begin
data = 8'h1;
\$display ("Original data = 'd%0d or 'b%0b", data, data);
for (i = 0; i < 8; i +=1 ) begin
\$display ("data << %0d = 'b%b", i, data << i);
end

data = 8'h80;
\$display ("Original data = 'd%0d or 'b%0b", data, data);
for (i = 0; i < 8; i +=1 ) begin \$display ("data >> %0d = 'b%b", i, data >> i);
end

data = 8'h1;
\$display ("
data >> 1 = 'b%b", data >> 1);
end
endmodule

```
```
Simulation Log
```ncsim> run
Original data = 'd1 or 'b00000001
data << 0 = 'b00000001
data << 1 = 'b00000010
data << 2 = 'b00000100
data << 3 = 'b00001000
data << 4 = 'b00010000
data << 5 = 'b00100000
data << 6 = 'b01000000
data << 7 = 'b10000000
Original data = 'd128 or 'b10000000
data >> 0 = 'b10000000
data >> 1 = 'b01000000
data >> 2 = 'b00100000
data >> 3 = 'b00010000
data >> 4 = 'b00001000
data >> 5 = 'b00000100
data >> 6 = 'b00000010
data >> 7 = 'b00000001

data >> 1 = 'b00000000
ncsim: *W,RNQUIE: Simulation is complete.

```