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The aim of this website is to connect verification engineers and provide an opportunity to share ideas and learn. You can also write your own blog post and not worry about maintaining it. It's also a platform for students to know more about chip design verification, languages and methodologies used in the industry during a project cycle.

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question on sequencer
If we have only one packet in sequence can we start our sequence directly on dri...
128 Hits
0 Votes
0 Replies
In UVM
Posted on Sunday, 30 September 2018
Canu please explain
Design a fsm for divisible by 5 Note: From lsb tosb...
150 Hits
0 Votes
0 Replies
Posted on Friday, 28 September 2018
How to time a thread inside a fork join?
i have a fork join with 3 threads. In the following example i want Configuration...
179 Hits
0 Votes
2 Replies
In UVM
Posted on Wednesday, 26 September 2018

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