Verilog Ports

Ports are a set of signals that act as inputs and outputs to a particular module and are the primary way of communicating with it. Think of a module as a fabricated chip placed on a PCB and it becomes quite obvious that the only way to communicate with the chip is through its pins. Ports are like pins and are used by the design to send and receive signals from the outside world.

Types of Ports

Ports are by default considered as nets of type wire.

Syntax

Ports declared as inout can act as both input and output.

	input  [net_type] [range] list_of_names; 	// Input port
	inout  [net_type] [range] list_of_names; 	// Input & Output port
	output [net_type] [range] list_of_names; 	// Output port driven by a wire
	output [var_type] [range] list_of_names; 	// Output port driven by a variable

Example

In the code shown below, there are three input ports, one output port and one inout port.

module  my_design ( input wire			clk,
                    input 					en,
                    input 					rw,
                    inout [15:0]	  data,
                    output 					int );
                    
	// Design behavior as Verilog code
	
endmodule

It is illegal to use the same name for multiple ports.

	input  aport;         // First declaration - valid
	input  aport;         // Error - already declared
	output aport;         // Error - already declared

Signed ports

The signed attribute can be attached to a port declaration or a net/reg declaration or both. Implicit nets are by default unsigned.

module ( input      a, 
                    b,
         output     c);
		 
	// ports a, b, and c are by default unsigned
endmodule

If either the net/reg declaration has a signed attribute, then the other shall also be considered signed.

	module ( input signed a, b,
	         output c);
		wire a, b;          // a, b are signed from port declaration
		reg signed c;       // c is signed from reg declaration
	endmodule

Port Variations

Verilog 1995

Verilog has undergone a few revisions and the original IEEE version in 1995 had the following way for port declaration. Here, module declaration had to first list the names of ports within the brackets and then direction of those ports defined later within the body of the module.

	
module test (a, b, c);
	
	input 	[7:0] a;            // inputs "a" and "b" are wires
	input 	[7:0] b;  
	output 	[7:0] c; 			// output "c" by default is a wire
	
	// Still, you can declare them again as wires to avoid confusion
	wire 	[7:0] a;
	wire 	[7:0] b;
	wire 	[7:0] c;
endmodule
	
	
module test (a, b, c);
	
	input  [7:0] a, b;
	output [7:0] c;           // By default c is of type wire
	
	// port "c" is changed to a reg type
	reg    [7:0] c;           
endmodule

Verilog 2001 onwards

ANSI-C style port naming was introduced in 2001 and allowed the type to be specified inside the port list.

module test ( input [7:0]	a,
                            b, 		// "b" is considered an 8-bit input
              output [7:0]  c);
			  
	// Design content			  
endmodule

module test ( input wire [7:0]	a, 	
              input wire [7:0]  b, 		
              output reg [7:0]  c);
			  
	// Design content
endmodule

If a port declaration includes a net or variable type, then that port is considered to be completely declared. It is illegal to redeclare the same port in a net or variable type declaration.

module test ( input      [7:0] a,       // a, e are implicitly declared of type wire
	          output reg [7:0] e );

   wire signed [7:0] a;     // illegal - declaration of a is already complete -> simulator dependent
   wire        [7:0] e;     // illegal - declaration of e is already complete
   
   // Rest of the design code
endmodule

If the port declaration does not include a net or variable type, then the port can be declared in a net or variable type declaration again.

module test ( input      [7:0] a,
              output     [7:0] e);
	              
     reg [7:0] e;              // Okay - net_type was not declared before
     
     // Rest of the design code
endmodule