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The case statement checks if the given expression matches one of the other expressions in the list and branches accordingly. It is typically used to implement a multiplexer. The if-else construct may not be suitable if there are many conditions to be checked and would synthesize into a priority encoder instead of a multiplexer.

Syntax

A Verilog case statement starts with the case keyword and ends with the endcase keyword. The expression within parantheses will be evaluated exactly once and is compared with the list of alternatives in the order they are written and the statements for which the alternative matches the given expression are executed. A block of multiple statements must be grouped and be within begin and end.

 
  // Here 'expression' should match one of the items (item 1,2,3 or 4)
  case (<expression>) 
    case_item1 :   <single statement>
    case_item2,
    case_item3 :   <single statement>
    case_item4 :   begin
                    <multiple statements>
                  end
    default    : <statement>
  endcase
 

If none of the case items match the given expression, statements within the default item is executed. The default statement is optional, and there can be only one default statement in a case statement. Case statements can be nested.

Execution will exit the case block without doing anything if none of the items match the expression and a default statement is not given.

Example

The design module shown below has a 2-bit select signal to route one of the three other 3-bit inputs to the output signal called out. A case statement is used to assign the correct input to output based on the value of sel. Since sel is a 2-bit signal, it can have 22 combinations, 0 through 3. The default statement helps to set output to 0 if sel is 3.

 
module my_mux (input       [2:0]   a, b, c,     // Three 3-bit inputs
                           [1:0]  sel,         // 2-bit select signal to choose from a, b, c
               output reg  [2:0]   out);       // Output 3-bit signal 
 
  // This always block is executed whenever a, b, c or sel changes in value
  always @ (a, b, c, sel) begin     
    case(sel)
      2'b00    : out = a;     // If sel=0, output is a
      2'b01    : out = b;     // If sel=1, output is b
      2'b10    : out = c;     // If sel=2, output is c
      default  : out = 0;     // If sel is anything else, out is always 0
    endcase
  end
endmodule
 

Hardware Schematic

The rtl code is elaborated to get a hardware schematic that represents a 4 to 1 multiplexer.

See that output is zero when sel is 3 and corresponds to the assigned inputs for other values.

Simulation Log
ncsim> run
[0]  a=0x4 b=0x1 c=0x1 sel=0b11 out=0x0
[10] a=0x5 b=0x5 c=0x5 sel=0b10 out=0x5
[20] a=0x1 b=0x5 c=0x6 sel=0b01 out=0x5
[30] a=0x5 b=0x4 c=0x1 sel=0b10 out=0x1
[40] a=0x5 b=0x2 c=0x5 sel=0b11 out=0x0
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

In a case statement, the comparison only succeeds when each bit of the expression matches one of the alternatives including 0, 1, x and z. In the example shown above, if any of the bits in sel is either x or z, the default statement will be executed because none of the other alternatives matched. In such a case, output will be all zeros.

Simulation Log

ncsim> run
[0] a=0x4 b=0x1 c=0x1 sel=0bxx out=0x0
[10] a=0x3 b=0x5 c=0x5 sel=0bzx out=0x0
[20] a=0x5 b=0x2 c=0x1 sel=0bxx out=0x0
[30] a=0x5 b=0x6 c=0x5 sel=0bzx out=0x0
[40] a=0x5 b=0x4 c=0x1 sel=0bxz out=0x0
[50] a=0x6 b=0x5 c=0x2 sel=0bxz out=0x0
[60] a=0x5 b=0x7 c=0x2 sel=0bzx out=0x0
[70] a=0x7 b=0x2 c=0x6 sel=0bzz out=0x0
[80] a=0x0 b=0x5 c=0x4 sel=0bxx out=0x0
[90] a=0x5 b=0x5 c=0x5 sel=0bxz out=0x0
ncsim: *W,RNQUIE: Simulation is complete.

If the case statement in design has x and z in the case item alternatives, the results would be quite different.

 
module my_mux (input      [2:0]   a, b, c,
                          [1:0]    sel,
              output reg  [2:0]   out);
 
  // Case items have x and z and sel has to match the exact value for
  // output to be assigned with the corresponding input
  always @ (a, b, c, sel) begin
    case(sel)
      2'bxz      :  out = a;
      2'bzx      :  out = b;
      2'bxx      :  out = c;
      default   :  out = 0;
    endcase
  end
endmodule
 
Simulation Log

ncsim> run
[0] a=0x4 b=0x1 c=0x1 sel=0bxx out=0x1
[10] a=0x3 b=0x5 c=0x5 sel=0bzx out=0x5
[20] a=0x5 b=0x2 c=0x1 sel=0bxx out=0x1
[30] a=0x5 b=0x6 c=0x5 sel=0bzx out=0x6
[40] a=0x5 b=0x4 c=0x1 sel=0bxz out=0x5
[50] a=0x6 b=0x5 c=0x2 sel=0bxz out=0x6
[60] a=0x5 b=0x7 c=0x2 sel=0bzx out=0x7
[70] a=0x7 b=0x2 c=0x6 sel=0bzz out=0x0
[80] a=0x0 b=0x5 c=0x4 sel=0bxx out=0x4
[90] a=0x5 b=0x5 c=0x5 sel=0bxz out=0x5
ncsim: *W,RNQUIE: Simulation is complete.

How is a case different from if-else ?

The case statement is different from if-else-if in two ways:

  • Expressions given in a if-else block are more general while in a case block, a single expression is matched with multiple items
  • case will provide a definitive result when there are X and Z values in an expression

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