Welcome ! This website will help YOU (recent graduates/professionals) learn verification languages like SystemVerilog and UVM. Register for free and access more content !

Hardware behavior cannot be implemented without conditional statements and other ways to control the flow of logic. Verilog has a set of control flow blocks and mechanisms to achieve the same.

if-else-if

This conditional statement is used to make a decision about whether certain statements should be executed or not. This is very similar to the if-else-if statements in C. If the expression evaluates to true, then the first statement will be executed. If the expression evaluates to false and if an else part exists, the else part will be executed.

Syntax
 
  // if statement without else part
  if (expression) 
    [statement]
 
  // if statment with an else part
  if (expression) 
    [statement]
  else 
    [statement]
 
  // if else for multiple statements should be
  // enclosed within "begin" and "end"
  if (expression) begin
    [multiple statements]
  end else begin
    [multiple statements]
  end
 
  // if-else-if statement
  if (expression)
    [statement]
  else if (expression)
    [statement]
  else 
    [statement]
 

The else part of an if-else is optional and can cause a confusion if an else is omitted in a nested if sequence. To avoid this confusion, it's easier to always associate the else to the previous if that lacks an else. Another way is to enclose statements within a begin-end block. The last else part handles none-of-the-above or default case where none of the other conditions were satisfied.

Click here to read more about if-else-if

Loops provide a way of executing single or multiple statements within a block one or more number of times. There are four different types of looping statements in Verilog.

forever loop

This will continuously execute the statements within the block.

 
  forever 
    [statement]
 
  forever begin
    [multiple statements]
  end
 

Example

 
module my_design;
  initial begin
    forever begin
      $display ("This will be printed forever, simulation can hang ...");
    end
  end
endmodule
 
Simulation Log

ncsim> run
This will be printed forever, simulation can hang ...
This will be printed forever, simulation can hang ...
...
...
This will be printed forever, simulation can hang ...
This will be printed forever, simulation can hang ...
This will be printed forever, simulation can hang ...
This will be printed forever, simulation can hang ...
Result reached the maximum of 5000 lines. Killing process.

repeat loop

This will execute statements a fixed number of times. If the expression evaluates to an X or Z, then it will be treated as zero and will not be executed at all.

 
  repeat ([num_of_times]) begin
    [statements]
  end
 
  repeat ([num_of_times]) @ ([some_event]) begin
    [statements]
  end
 

Example

 
module my_design;
  initial begin
    repeat(4) begin
      $display("This is a new iteration ...");
    end
  end
endmodule
 
Simulation Log

ncsim> run
This is a new iteration ...
This is a new iteration ...
This is a new iteration ...
This is a new iteration ...
ncsim: *W,RNQUIE: Simulation is complete.

while loop

This will execute statements as long as an expression is true and will exit once the condition becomes false. If the condition is false from the start, statements will not be executed at all.

 
  while (expression) begin
    [statements]
  end
 

Example

 
module my_design;
    integer i = 5;
 
  initial begin
      while (i > 0) begin
        $display ("Iteration#%0d", i);
        i = i - 1;
      end
  end
endmodule
 
Simulation Log

ncsim> run
Iteration#5
Iteration#4
Iteration#3
Iteration#2
Iteration#1
ncsim: *W,RNQUIE: Simulation is complete.

for loop

 
  for ( initial_assignment; condition; increment_variable) begin
    [statements]
  end
 

This will control statements using a three-step process:

  • Initialize a loop counter variable
  • Evaluate the expression, usually involving the loop counter variable
  • Increment loop counter variable so that at a later time the expression will become false and loop will exit.

Example

 
module my_design;
    integer i = 5;
 
  initial begin
      for (i = 0; i < 5; i = i + 1) begin
        $display ("Loop #%0d", i);
      end
    end
endmodule
 
Simulation Log

ncsim> run
Loop #0
Loop #1
Loop #2
Loop #3
Loop #4
ncsim: *W,RNQUIE: Simulation is complete.

Click here to read more about for loops.

Was this article helpful ?



You consent to our cookies if you continue to use our website. To know more about cookies, see our privacy policy. I accept cookies from this site.

Agree