An adder is a digital component that performs addition of two numbers. Its the main component inside an ALU of a processor and is used to increment addresses, table indices, buffer pointers and in a lot of other places where addition is required.

A full adder adds a carry input along with other input binary numbers to produce a sum and a carry output.

A B Cin Cout Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

## Design

An example of a 4-bit adder is shown below which accepts two binary numbers through the signals a and b which are both 4-bits wide. Since an adder is a combinational circuit, it can be modeled in Verilog using a continuous assignment with `assign` or an `always` block with a sensitivity list that comprises of all inputs. The code shown below is that of the former approach.

```  ```

module fulladd (  input [3:0] a,
input [3:0] b,
input c_in,
output c_out,
output [3:0] sum);

assign {c_out, sum} = a + b + c_in;
endmodule

```
```

The code shown below uses an `always` block which gets executed whenever any of its inputs change value.

```  ```

module fulladd (  input [3:0] a,
input [3:0] b,
input c_in,
output reg c_out,
output reg [3:0] sum);

always @ (a or b or c_in) begin
{c_out, sum} = a + b + c_in;
end
endmodule

```
```

## Hardware Schematic ## Testbench

```  ```

// 1. Declare testbench variables
reg [3:0] a;
reg [3:0] b;
reg c_in;
wire [3:0] sum;
integer i;

// 2. Instantiate the design and connect to testbench variables
.b (b),
.c_in (c_in),
.c_out (c_out),
.sum (sum));

// 3. Provide stimulus to test the design
initial begin
a <= 0;
b <= 0;
c_in <= 0;

\$monitor ("a=0x%0h b=0x%0h c_in=0x%0h c_out=0x%0h sum=0x%0h", a, b, c_in, c_out, sum);

// Use a for loop to apply random values to the input
for (i = 0; i < 5; i = i+1) begin
#10 a <= \$random;
b <= \$random;
c_in <= \$random;
end
end
endmodule

```
```

Note that when a and b add up to give a number more than 4 bits wide, the sum rolls over to zero and c_out becomes 1. For example, the line highlighted in yellow adds up to give 0x11 and the lower 4 bits get assigned to sum and bit#4 to c_out.

Simulation Log
```ncsim> run
a=0x0 b=0x0 c_in=0x0 c_out=0x0 sum=0x0
a=0x4 b=0x1 c_in=0x1 c_out=0x0 sum=0x6
a=0x3 b=0xd c_in=0x1 c_out=0x1 sum=0x1
a=0x5 b=0x2 c_in=0x1 c_out=0x0 sum=0x8
a=0xd b=0x6 c_in=0x1 c_out=0x1 sum=0x4
a=0xd b=0xc c_in=0x1 c_out=0x1 sum=0xa
ncsim: *W,RNQUIE: Simulation is complete.

``` 