Verilog Interview Set 1

Write Verilog code to swap contents of two registers with and without a temporary register?

Swapping Contents of Two Registers using a Temporary Register:

always @(posedge clk) begin
	temp = b;
	b = a;
	temp = a;
end
 

Swapping contents of two registers without a temporary register:

always @(posedge clk) begin
	a <= b;
    b <= a;
end

This is because a non-blocking assignment captures the RHS of all statements in a given delta cycle and assigns them at the end of the cycle. Read more on Verilog Blocking & Non-Blocking statements.

Elaborate on the file operation support in Verilog.

Verilog supports file I/O operations - reading from and writing into files. Verilog file operations work very similar to those of C programming language. Some of the commonly used Verilog system tasks are $fopen, $fscanf, $fdisplay, $fwrite, $fclose.

Read more on Verilog File IO Operations.

Difference between inter statement and intra statement delay?

Inter statement delay refers to the delay between two statements. It represents the time difference between the completion of one statement and the start of another statement.

Intra statement delay refers to the delay within a single statement. It represents the time difference between the start of a statement and the execution of a specific operation within that statement.

Read more on Verilog Inter and Intra Assignment Delay.

What is delta simulation time?

Delta delay is a special type of delay in Verilog, which is used to model the execution of hardware events that take zero simulation time. It is also known as zero delay.

In Verilog, the delta delay is the smallest delay that can be specified. It represents the smallest unit of simulation time in Verilog. A delta delay can occur when an event is triggered immediately after the completion of the current statement. In this case, the simulation engine does not advance the simulation time, as there is no actual delay between the two events. Instead, the simulation time stays the same, and the event is executed in a single simulation time step.

Delta delay is used to model combinational logic and some types of synchronous logic that do not introduce any delay between input and output. For example, when an input signal changes, a combinational block may immediately process this input and produce an output, with no delay. Read more on Verilog Scheduling Semantics.

What is meant by inferring latches and how can you avoid it?

In Verilog, inferring latches refers to the unintentional generation of latches when synthesizing an RTL design code. A latch is a sequential logic circuit element that stores a signal value until the next clock cycle. Latches are sometimes undesirable in digital circuit design because they can result in difficult to control circuit behavior, power consumption and unintended glitches.

Inferring latches can occur when a designer does not assign a value to a signal under every possible condition. For example, if a designer creates a combinational logic circuit that assigns a value to a signal only under certain conditions, but does not assign a value to that signal under other conditions, the synthesis tool will infer a latch to store that signal value when it is not being explicitly set by the design. A latch is inferred when the output of combinatorial logic has undefined states, that is it must hold its previous value.

// "z" missing in the sensitivity list
always @(x or y) 
  out = x & y | z;

// Value of "out" when x=0 is not defined, and hence previous value has to be held
always @* begin
  if (x) begin
    out = y & z;
  end
end

To avoid inferring latches, a designer should ensure that every signal in the design has a deterministic value assigned to it under all possible conditions. Using if-else constructs or case statements, with a default condition to ensure that every signal is assigned a value, can help to avoid inferring latches. A designer should also avoid inferring latches by writing code that applies a defined value to inputs without the need of latch.

Which will be updated first - variables or signals ?

In Verilog, signals are updated before variables. Signals are used to represent wires or registers in a design, while variables are used to represent local storage elements in procedural blocks such as always blocks or initial blocks.

When an event occurs, such as a clock edge, signals are updated first based on the new input values. Then, the updated signal values that are registered and stored internally by the hardware will be directed to variable storage. Therefore, if multiple signals and variables are being updated within the same procedural block, the signals are updated first and then the variables are updated based on the new signal values.

It is important to keep in mind the order of updates of signals and variables while writing the Verilog code. This can help to ensure that the design behaves as expected and can prevent unexpected delays or glitches in the circuit.

Why is it necessary to list all inputs in the sensitivity list of a combinational circuit ?

It is necessary to list all input signals in the sensitivity list of a combinational circuit in Verilog because the sensitivity list specifies the events that will cause the corresponding always block to execute.

always @ (a, b)
begin
    c = a & b;
end

This always block is sensitive to the input signals a and b . Whenever either a or b changes, the always block will execute and compute the output c . Else, it may result in a latch as discussed above.

Read more on Combinational Logic with always.

What are the main differences between VHDL and Verilog ?

VHDL (VHSIC Hardware Description Language) and Verilog are two major hardware description languages used for designing digital circuits. The main differences between VHDL and Verilog are as follows:

• Syntax: VHDL uses a verbose syntax that reads like natural language, while Verilog uses a more concise syntax that is similar to C programming language.
• Data Types: VHDL has a rich set of data types, including arrays, records, and access types, and provides support for user-defined types. Verilog, on the other hand, has a limited set of data types, including wires and registers.
• Modeling: VHDL is more focused on concurrent process modeling, with constructs like processes and components, while Verilog is more focused on gate-level modeling, with constructs like gates and always blocks.
• Libraries: VHDL uses a library-based approach to manage components and packages, while Verilog provides a module-based approach to component instantiation.
• Testing: VHDL provides a clear distinction between design and testbench code, with separate files for each, while Verilog allows for testbench code to be intermixed with design code.

Read more on Verilog syntax.

Give some examples of commonly used Verilog system tasks and their purposes.

System tasks are predefined functions in Verilog that can perform complex operations that would otherwise be difficult to implement in a hardware description language. Some commonly used system tasks include:

These system tasks can be extremely helpful for debugging, testing, and verification of Verilog programs. Read more on Verilog Display Tasks, Verilog Math Functions and Verilog File IO Operations.

Write a Verilog code for synchronous and asynchronous reset.

Here are examples of Verilog code for implementing synchronous and asynchronous resets:

Synchronous Reset:

module synchronous_reset(
    input clk,
    input reset_n,
    //input/output ports
    // ...
    )
    
    reg [7:0] data;
    
    always @(posedge clk)
    begin
        if (!reset_n) //active low reset
            data <= 8'b0;
        else
            data <= //update data based on input ports
    end
    
    //output ports
    // ...
endmodule

Asynchronous Reset:

module asynchronous_reset(
    input clk,
    input reset_n,
    //input/output ports
    // ...
    )
    
    reg [7:0] data;
    
    always @(posedge clk or negedge reset_n)
    begin
        if (!reset_n) //active low reset
            data <= 8'b0;
        else
            data <= //update data based on input ports
    end
    
    //output ports
    // ...
endmodule

In the synchronous reset module, the input reset_n is synchronized with the clock signal using an edge-triggered flip-flop. The reset condition is checked on the rising edge of the clock, and if reset_n is low, the data is reset to 0. Otherwise, data is updated based on input ports.

In the asynchronous reset module, the input reset_n is checked on both rising and falling edges of the clock, and if reset_n is low, the data is reset to 0 regardless of the current clock state.