Straight Ring Counter

Design

 
module ring_ctr  #(parameter WIDTH=4) 
  (  
  input clk,                
  input rstn,
    output reg [WIDTH-1:0] out
  );    
 
  always @ (posedge clk) begin
      if (!rstn)
         out <= 1;
      else begin
        out[WIDTH-1] <= out[0];
        for (int i = 0; i < WIDTH-1; i=i+1) begin
          out[i] <= out[i+1];
        end
      end
  end
endmodule
 

Testbench

 
module tb;
  parameter WIDTH = 4;
 
  reg clk;
  reg rstn;
  wire [WIDTH-1:0] out;
 
  ring_ctr   u0 (.clk (clk),
                .rstn (rstn),
                .out (out));
 
  always #10 clk = ~clk;
 
  initial begin
    {clk, rstn} <= 0;
 
    $monitor ("T=%0t out=%b", $time, out);
    repeat (2) @(posedge clk);
    rstn <= 1;
    repeat (15) @(posedge clk);
    $finish;
  end
endmodule
 
Simulation Log

ncsim> run
T=0 out=xxxx
T=10 out=0001
T=50 out=1000
T=70 out=0100
T=90 out=0010
T=110 out=0001
T=130 out=1000
T=150 out=0100
T=170 out=0010
T=190 out=0001
T=210 out=1000
T=230 out=0100
T=250 out=0010
T=270 out=0001
T=290 out=1000
T=310 out=0100
Simulation complete via $finish(1) at time 330 NS + 0

Click to try this example in a simulator!   

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