Universal Verification Methodology (UVM) is a standard to enable faster development and reuse of verification environments and verification IP (VIP) throughout the industry.

It is a set of class libraries defined using the syntax and semantics of SystemVerilog (IEEE 1800) and is now an IEEE standard. The main idea behind UVM is to help companies develop modular, reusable, and scalable testbench structures by providing an API framework that can be deployed across multiple projects.


Ch#1: Introduction Learn about UVM, how to install UVM library and about all basic features of UVM
Ch#2: Common Utilites Learn about main common utility methods like print, copy, compare and how to use them with utility macros and in-built functions
Ch#3: Testbench Structure Learn how to build basic testbench components like driver, monitor, scoreboard using UVM library classes
Ch#4: UVM Phases Learn about how testbench is built, and the different phases of simulation within UVM framework
Ch#5: Factory Learn about the concepts of factory, and how UVM makes testbench configurable using factory override methods
Ch#6: Stimulus Generation Learn about UVM sequences, how to define and start sequences and generate complex stimulus to drive DUT
Ch#5: Reporting Infrastructure Learn about UVM reporting macros, functions, verbosity settings and their control
Ch#6: Config Database Learn how to pass configurations and settings from top layers in testbench to lower layers using config_db mechanisms
Ch#7: TLM Learn about how components connect to each other and send class objects within the UVM framework
Ch#8: Register Layer Learn how to develop register model, adapters, predictors and environment to make use of write/read API to access DUT registers
Ch#9: Misc Classes Learn about other UVM classes that support flexible and scalable testbench structures

UVM is mainly derived from Open Verification Methodology (OVM) and is supported by multiple EDA vendors like Synopsys, Cadence, Mentor and Aldec. The UVM class library provides generic utilities like configuration databases, TLM and component hierarchy in addition to data automation features like copy, print, and compare. It brings in a layer of abstraction where every component in the verification environment has a specific role. For example, a driver class object will be responsible only for driving signals to the design, while a monitor simply monitors the design interface and does not drive signals to that interface.

The image below shows how a typical verification environment is built by extending readily available UVM classes which are denoted by uvm_* prefix. These components already have the necessary code that will let them connect between each other, handle data packets and work synchronously with others.

It also goes through many revisions where new features are added and some older ones deprecated. The reference manual for UVM can be obtained here and contains description on class hierarchy, functions and tasks. It might become overwhelming for new users because of the extensive API available for implementation. So, it requires a more disciplined approach to understand the framework part by part. Hopefully, you'll find the information in these pages useful.

Click here to refresh SystemVerilog before diving into UVM.

Jump to Introduction and follow the links in the sidebar to the left.

Or go to Hello UVM ! to run an example, and do a walkthrough of adding components one by one.


You can browse through 100+ example codes in CodeHub.