It's always best to get started using a very simple example, and none serves the purpose best other than "Hello World !".

 
// Single line comments start with double forward slash "//"
// Verilog code is always written inside modules, and each module represents a digital block with some functionality
module tb;
 
  // Initial block is another construct typically used to initialize signal nets and variables for simulation
  initial
    // Verilog supports displaying signal values to the screen so that designers can debug whats wrong with their circuit
    // For our purposes, we'll simply display "Hello World" 
    $display ("Hello World !");
endmodule
 

A module called tb with no input-output ports act as the top module for the simulation. The initial block starts and executes the first statement at time 0 units. $display is a Verilog system task used to display a formatted string to the console and cannot be synthesized into hardware. Its primarily used to help with testbench and design debug. In this case, the text message displayed onto the screen is "Hello World !".

Simulation Log
ncsim> run
Hello World !
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

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