What is UVM ?
UVM stands for Universal Verification Methodology. It is a standardized methodology for verifying digital designs and systems-on-chip (SoCs) in the semiconductor industry. UVM is built on top of the SystemVerilog language and provides a framework for creating modular, reusable testbench components that can be easily integrated into the design verification process. It also includes a set of guidelines and best practices for developing testbenches, as well as a methodology for running simulations and analyzing results.
UVM has become the de facto standard for design verification in the semiconductor industry, and is widely used by chip designers and verification engineers to verify the correctness and functionality of their designs.
What was used before UVM ?
OVM (Open Verification Methodology) was introduced in 2008 as an open-source verification methodology for digital designs and systems-on-chip (SoCs) and was based on SystemVerilog
UVM was introduced in 2011 as a successor to OVM, and it built upon the concepts and principles of OVM. UVM was designed to be a more standardized and flexible methodology that could be easily adapted to different verification environments and use cases.
Why was OVM replaced by UVM ?
This was done mainly for the following reasons :
- Standardization: OVM was an open-source methodology that lacked a formal standard, which made it difficult for different organizations and tools to interoperate effectively. UVM was designed to be a more standardized methodology, with a well-defined standard that could be adopted by the entire semiconductor industry.
- Flexibility: OVM was designed primarily for transaction-level modeling (TLM), which limited its applicability to other verification scenarios, such as register-transfer level (RTL) modeling. UVM was designed to be more flexible, with support for both TLM and RTL modeling, as well as other verification scenarios.
- Reusability: OVM provided a set of pre-defined classes and components for creating testbenches, but these components were not always modular and reusable. UVM was designed to be more modular and reusable, with a clear separation between testbench components and the design-under-test (DUT).
- Maintainability: OVM was not always easy to maintain or update, as changes to the methodology could affect existing testbenches and components. UVM was designed to be more maintainable, with a clear separation between the methodology and the implementation of testbenches and components.
What does UVM contain ?
It contains a set of pre-defined classes and methods that enable users to create modular, reusable testbench components for verifying digital designs and systems-on-chip (SoCs). Some of the key components of UVM include:
- Testbench Components: UVM provides a set of base classes that can be extended to create testbench components, such as drivers, monitors, scoreboards, and agents.
- Transactions: Transactions are used to model the communication between the design-under-test (DUT) and the testbench. UVM provides a transaction class that can be extended to create transaction objects that carry information between the DUT and the testbench.
- Phases: UVM defines a set of simulation phases that enable users to control the order in which testbench components are created, initialized, and executed.
- Messaging and Reporting: UVM provides a messaging and reporting infrastructure that enables users to output information about the simulation, such as warnings, errors, and debug information.
- Configuration: UVM provides a configuration database that allows users to store and retrieve configuration information for testbench components.
- Functional Coverage: UVM provides a mechanism for tracking functional coverage, which is used to ensure that the design has been thoroughly tested.
- Register Abstraction Layer: UVM provides a register abstraction layer (RAL) that simplifies the process of creating and accessing register maps.
For example, the image below shows how a typical verification environment is built by extending readily available UVM classes which are denoted by
uvm_* prefix. These components already have the necessary code that will let them connect between each other, handle data packets and work synchronously with others.
It also undergoes many revisions where new features are added and some older ones deprecated. The reference manual for UVM can be obtained here and contains description on class hierarchy, functions and tasks. It might be overwhelming for new users to understand UVM because of its extensive API. So it requires a more disciplined approach to understand the framework part by part. Hopefully, you'll find the information in these pages useful.
What are some of the prerequisites for learning UVM ?
UVM is based on the SystemVerilog language, so you should have a basic understanding of SystemVerilog syntax and constructs, such as classes, inheritance, and randomization. This knowledge will help you understand the UVM code and develop your own UVM-based testbenches.
You should be familiar with simulation tools, such as Cadence Incisive, Mentor Graphics Questa, or Synopsys VCS, which are commonly used in digital design verification. This knowledge will help you run and debug UVM-based testbenches using these tools.
You should have a basic understanding of verification methodologies, such as directed testing, constrained random testing, and coverage-driven verification. This knowledge will help you understand the role of UVM in the overall verification process and how to use UVM to implement these methodologies.
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