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The conditional if else statement is used to make a decision about whether a statement is executed.

Click here to refresh if else if in Verilog !

SystemVerilog introduced the following if else constructs for violation checks.

unique-if, unique0-if

unique-if evaluates conditions in any order and does the following :

  • report an error when none of the if conditions match unless there is an explicit else.
  • report an erorr when there is more than 1 match found in the if else conditions

Unlike unique-if, unique0-if does not report a violation if none of the conditions match

No else block for unique-if

 
module tb;
  int x = 4;
 
    initial begin
        // This if else if construct is declared to be "unique"
    // Error is not reported here because there is a "else"
        // clause in the end which will be triggered when none of
        // the conditions match
      unique if (x == 3) 
          $display ("x is %0d", x);
      else if (x == 5)
          $display ("x is %0d", x);
        else
          $display ("x is neither 3 nor 5");      
 
        // When none of the conditions become true and there
        // is no "else" clause, then an error is reported
      unique if (x == 3) 
          $display ("x is %0d", x);
      else if (x == 5)
          $display ("x is %0d", x);
    end
endmodule  
 
Simulation Log
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Unique if violation:  Every if clause was false.
            File: ./testbench.sv, line = 18, pos = 13
           Scope: tb
            Time: 0 FS + 1

ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Multiple matches in unique-if

 
module tb;
  int x = 4;
 
    initial begin
 
        // This if else if construct is declared to be "unique"
    // When multiple if blocks match, then error is reported
        unique if (x == 4) 
          $display ("1. x is %0d", x);
        else if (x == 4)
          $display ("2. x is %0d", x);
        else
          $display ("x is not 4");
    end
endmodule
 
Simulation Log
ncsim> run
1. x is 4
ncsim: *W,MCONDE: Unique if violation:  Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.
            File: ./testbench.sv, line = 8, pos = 15
           Scope: tb
            Time: 0 FS + 1

ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

priority-if

priority-if evaluates all conditions in sequential order and a violation is reported when:

  • None of the conditions are true or if there's no else clause to the final if construct

No else clause in priority-if

 
module tb;
  int x = 4;
 
    initial begin
        // This if else if construct is declared to be "unique"
    // Error is not reported here because there is a "else"
        // clause in the end which will be triggered when none of
        // the conditions match
      priority if (x == 3) 
          $display ("x is %0d", x);
      else if (x == 5)
          $display ("x is %0d", x);
        else
          $display ("x is neither 3 nor 5");      
 
        // When none of the conditions become true and there
        // is no "else" clause, then an error is reported
      priority if (x == 3) 
          $display ("x is %0d", x);
      else if (x == 5)
          $display ("x is %0d", x);
    end
endmodule  
 
Simulation Log
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Priority if violation:  Every if clause was false.
            File: ./testbench.sv, line = 18, pos = 15
           Scope: tb
            Time: 0 FS + 1

ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Exit after first match in priority-if

 
module tb;
  int x = 4;
 
    initial begin    
        // Exits if-else block once the first match is found
        priority if (x == 4)
          $display ("x is %0d", x);
      else if (x != 5)
          $display ("x is %0d", x);
    end
endmodule  
 
Simulation Log
ncsim> run
x is 4
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

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