SystemVerilog Clocking Blocks
Module ports and interfaces by default do not specify any timing requirements or synchronization schemes between signals. A clocking block defined between
endcocking does exactly that. It is a collection of signals synchronous with a particular clock and helps to specify the timing requirements between the clock and the signals.
This would allow test writers to focus more on transactions rather than worry about when a signal will interact with respect to a clock. A testbench can have many clocking blocks, but only one block per clock.
[default] clocking [identifier_name] @ [event_or_identifier] default input #[delay_or_edge] output #[delay_or_edge] [list of signals] endclocking
The delay_value represents a skew of how many time units away from the clock event a signal is to be sampled or driven. If a
default skew is not specified, then all input signals will be sampled
#1step and output signlas driven
0ns after the specified event.
clocking ckb @ (posedge clk); default input #1step output negedge; input ...; output ...; endclocking clocking ck1 @ (posedge clk); default input #5ns output #2ns; input data, valid, ready = top.ele.ready; output negedge grant; input #1step addr; endclocking
Note the following:
- A clocking block called ck1 is created which will be active on the positive edge of clk
- By default, all input signals within the clocking block will be sampled 5ns before and all output signals within the clocking block will be driven 2ns after the positive edge of the clock clk
- data, valid and ready are declared as inputs to the block and hence will be sampled 2ns before the posedge of clk
- grant is an output signal to the block with its own time requirement. Here grant will be driven at the negedge of clk instead of the default posedge.
Use within an interface
Simply put, a clocking block encapsulates a bunch of signals that share a common clock. Hence declaring a clocking block inside an interface can help save the amount of code required to connect to the testbench and may help save time during development.
Signal directions inside a clocking block are with respect to the testbench and not the DUT.