SystemVerilog gives us two constructs to declare conditional relations - implication and if else.
The following code snippet shows both styles
// Implication operator "->" tells that len should be
// greater than 10 when mode is equal to 2
constraint c_mode { mode == 2 -> len > 10; }
// Same thing can be achieved with "if-else" construct
constraint c_mode { if (mode == 2)
len > 10;
}
Note that mode need not be 2 for all values of len greater than 10. However, the constraint says that len should be greater than 10 if mode is 2.
Example
class ABC;
rand bit [2:0] mode;
rand bit [3:0] len;
constraint c_mode { mode == 2 -> len > 10; }
endclass
module tb;
initial begin
ABC abc = new;
for(int i = 0; i < 10; i++) begin
abc.randomize();
$display ("mode=%0d len=%0d", abc.mode, abc.len);
end
end
endmodule
The simulation results show that mode need not have a value of 2 when len is greater than 10.
ncsim> run mode=1 len=11 mode=6 len=3 mode=3 len=9 mode=7 len=11 mode=3 len=15 mode=2 len=12 mode=3 len=6 mode=2 len=12 mode=4 len=9 mode=7 len=13 ncsim: *W,RNQUIE: Simulation is complete.
Implication Operator
An implication operator -> can be used in a constraint expression to show conditional relationship between two variables.
If the expression on the LHS of -> operator is true, then the constraint expression on the RHS will be satisfied. If the LHS is not true, then RHS constraint expression is not considered.
Example
class ABC;
rand bit [3:0] mode;
rand bit mod_en;
// If 5 <= mode <= 11, mod_en should be 1
constraint c_mode { mode inside {[4'h5:4'hB]} -> mod_en == 1; }
endclass
module tb;
initial begin
ABC abc = new;
for (int i = 0; i < 10; i++) begin
abc.randomize();
$display ("mode=0x%0h mod_en=0x%0h", abc.mode, abc.mod_en);
end
end
endmodule
Note that mod_en is 1 whenever the LHS expression for mode is inside 4'h5 and 4'hB. However, mod_en can be randomized to any value if the LHS evaluates to false.
ncsim> run mode=0xf mod_en=0x1 mode=0x9 mod_en=0x1 mode=0x3 mod_en=0x1 mode=0xe mod_en=0x1 mode=0x1 mod_en=0x1 mode=0x0 mod_en=0x0 mode=0x1 mod_en=0x0 mode=0xe mod_en=0x0 mode=0x5 mod_en=0x1 mode=0x0 mod_en=0x0 ncsim: *W,RNQUIE: Simulation is complete.
if-else Constraint
The if-else constraint provides an option to specify the else part of a conditional expression. If the conditional expression is true, then all of the constraints specified in the the first constraint set shall be satisfied. Otherwise, all of the constraints in the optional else part will be satisfied.
Nested if-else blocks are allowed and multiple constraint statements require them to be enclosed in curly braces { }. This is similar to the begin-end used in a procedural block like initial and always. However, constraints are classified as declarative code and hence require curly braces instead.
Example
In the code shown below, the first if block checks whether mode is inside 5 and 11. If this condition is true, then mod_en should be constrained to 1 and if it is false, then the else part is executed. There is another if-else block within the else part which checks if mode is 1 and tries to satisfy the constraints mentioned in the appropriate parts.
class ABC;
rand bit [3:0] mode;
rand bit mod_en;
constraint c_mode {
// If 5 <= mode <= 11, then constrain mod_en to 1
// This part only has 1 statement and hence do not
// require curly braces {}
if (mode inside {[4'h5:4'hB]})
mod_en == 1;
// If the above condition is false, then do the following
else {
// If mode is constrained to be 1, then mod_en should be 1
if ( mode == 4'h1) {
mod_en == 1;
// If mode is any other value than 1 and not within
// 5:11, then mod_en should be constrained to 0
} else {
mod_en == 0;
}
}
}
endclass
module tb;
initial begin
ABC abc = new;
for (int i = 0; i < 10; i++) begin
abc.randomize();
$display ("mode=0x%0h mod_en=0x%0h", abc.mode, abc.mod_en);
end
end
endmodule
ncsim> run mode=0xb mod_en=0x1 mode=0x1 mod_en=0x1 mode=0x6 mod_en=0x1 mode=0x7 mod_en=0x1 mode=0x2 mod_en=0x0 mode=0x2 mod_en=0x0 mode=0x2 mod_en=0x0 mode=0x9 mod_en=0x1 mode=0x7 mod_en=0x1 mode=0x8 mod_en=0x1 ncsim: *W,RNQUIE: Simulation is complete.
