SystemVerilog forever loop
forever loop runs forever, or for infinite time.
forever // Single statement forever begin // Multiple statements end
forever loop is similar to the code shown below in Verilog. Both run for infinite simulation time, and is important to have a delay element inside them.
An always or forever block without a delay element will hang in simulation !
always // Single statement always begin // Multiple statements end
In SystemVerilog, an
always block cannot be placed inside classes and other SystemVerilog procedural blocks. Instead we can use a
forever loop to achieve the same effect.
The pseudo code shown below mimics the functionality of a monitor in testbench that is once started and allowed to run as long as there is activity on the bus it monitors.
class Monitor; virtual task run(); forever begin @(posedge vif.clk); if (vif.write & vif.sel) // Capture write data if (!vif.write & vif.sel) // Capture read data end endtask endclass module tb; Monitor mon; // Start the monitor task and allow it to continue as // long as there is activity on the bus initial begin fork mon.run(); join_none end endmodule