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A SystemVerilog case statement checks whether an expression matches one of a number of expressions and branches appropriately. The behavior is the same as in Verilog.

Click here to learn about Verilog case statements !

unique,unique0 case

All case statements can be qualified by unique or unique0 keywords to perform violation checks like we saw in if-else-if construct.

unique and unique0 ensure that there is no overlapping case items and hence can be evaluated in parallel. If there are overlapping case items, then a violation is reported.

  • If more than one case item is found to match the given expression, then a violation is reported and the first matching expression is executed
  • If no case item is found to match the given expression, then a violation is reported only for unqiue

unique0 does not report a violation if no items match the expression

unique : No items match for given expression

 
module tb;
  bit [1:0]   abc;
 
  initial begin
    abc = 1;
 
    // None of the case items match the value in "abc"
    // A violation is reported here
    unique case (abc)
      0 : $display ("Found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule
 
Simulation Log
ncsim> run
ncsim: *W,NOCOND: Unique case violation:  Every case item expression was false.
            File: ./testbench.sv, line = 9, pos = 14
           Scope: tb
            Time: 0 FS + 1

ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

unique : More than one case item matches

 
module tb;
  bit [1:0]   abc;
 
  initial begin
    abc = 0;
 
    // Multiple case items match the value in "abc"
    // A violation is reported here
    unique case (abc)
      0 : $display ("Found to be 0");
      0 : $display ("Again found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule
 
Simulation Log
ncsim> run
Found to be 0
ncsim: *W,MCONDE: Unique case violation:  Multiple matching case item expressions at {line=10:pos=6 and line=11:pos=6}.
            File: ./testbench.sv, line = 9, pos = 14
           Scope: tb
            Time: 0 FS + 1

ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

priority case

module tb;
  bit [1:0] 	abc;
  
  initial begin
    abc = 0;
    
    // First match is executed
    priority case (abc)
      0 : $display ("Found to be 0");
      0 : $display ("Again found to be 0");
      2 : $display ("Found to be 2");
    endcase
  end
endmodule
Simulation Log
ncsim> run
Found to be 0
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

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