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The inside keyword in SystemVerilog allows to check if a given value lies within the range specified using the inside phrase. This can also be used inside if and other conditional statements in addition to being used as a constraint.

Syntax

 
  <variable> inside {<values or range>}
 
  // Inverted "inside"
  !(<variable> inside {<values or range>})
 

For example,

 
  m_var inside {4, 7, 9}     // Check if m_var is either 4,7 or 9
  m_var inside {[10:100]}   // Check if m_var is between 10 and 100 inclusive
 

When used in conditional statements

In the following example, inside operator is used both in an if else statement and a ternary operator. flag gets the value 1 if the randomized value of m_data lies within 4 to 9, including 4 and 9. If not, flag gets 0.

Similarly, if else block uses the same operator and prints a display message.

 
module tb;
  bit [3:0]   m_data;
  bit     flag;
 
  initial begin
    for (int i = 0; i < 10; i++) begin
      m_data = $random;
 
      // Used in a ternary operator
      flag = m_data inside {[4:9]} ? 1 : 0;
 
      // Used with "if-else" operators
      if (m_data inside {[4:9]})
        $display ("m_data=%0d INSIDE [4:9], flag=%0d", m_data, flag);
      else 
        $display ("m_data=%0d outside [4:9], flag=%0d", m_data, flag);
 
 
    end
  end
endmodule
 
Simulation Log
ncsim> run
m_data=4 INSIDE [4:9], flag=1
m_data=1 outside [4:9], flag=0
m_data=9 INSIDE [4:9], flag=1
m_data=3 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
m_data=5 INSIDE [4:9], flag=1
m_data=2 outside [4:9], flag=0
m_data=1 outside [4:9], flag=0
m_data=13 outside [4:9], flag=0
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Used in constraints

The inside operator is quite useful in constraints and makes code shorter and more readable.

 
class ABC;
  rand bit [3:0]   m_var;
 
  // Constrain m_var to be either 3,4,5,6 or 7
  constraint c_var { m_var inside {[3:7]}; }
endclass
 
module tb;
  initial begin
    ABC abc = new();
    repeat (5) begin
      abc.randomize();
      $display("abc.m_var = %0d", abc.m_var);
    end
 
  end
endmodule
 

See that all values of m_var lies inside the given range.

Simulation Log
ncsim> run
abc.m_var = 7
abc.m_var = 6
abc.m_var = 6
abc.m_var = 3
abc.m_var = 4
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Inverted inside

The opposite of what the inside operator does can be achieved by placing a not symbol ! before it. This is applicable for both constraints and conditional statements. The following example is the same as we saw before except that its constraint has been tweaked to reflect an inverted inside statement.

 
class ABC;
  rand bit [3:0]   m_var;
 
  // Inverted inside: Constrain m_var to be outside 3 to 7
  constraint c_var { !(m_var inside {[3:7]}); }
endclass
 
module tb;
  initial begin
    ABC abc = new();
    repeat (5) begin
      abc.randomize();
      $display("abc.m_var = %0d", abc.m_var);
    end
 
  end
endmodule
 

See that all values of m_var lies inside the given range.

Simulation Log
ncsim> run
abc.m_var = 1
abc.m_var = 12
abc.m_var = 0
abc.m_var = 14
abc.m_var = 10
ncsim: *W,RNQUIE: Simulation is complete.

Click to try this example in a simulator!   

Practical Example

Say we have a memory located between the address range 0x4000 and 0x5FFF, which is partitioned into two. The first part is used to store instructions and the second part to store data. Say we want to randomize the address for data such that the address falls within the data part of memory, we can easily use the inside operator.

 
class Data;
  rand bit [15:0]   m_addr;
 
  constraint c_addr   { m_addr inside {[16'h4000:16'h4fff]}; }
endclass
 
module tb;
  initial begin
    Data data = new();
    repeat (5) begin
      data.randomize();
      $display ("addr = 0x%0h", data.m_addr);
    end
  end
endmodule
 
Simulation Log
ncsim> run
addr = 0x48ef
addr = 0x463f
addr = 0x4612
addr = 0x4249
addr = 0x4cee
ncsim: *W,RNQUIE: Simulation is complete.

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