SystemVerilog Assertions with time delay
If a is not high on any given clock cycle, the sequence starts and fails on the same cycle. However, if a is high on any clock, the assertion starts and succeeds if b is high 2 clocks later. It fails if b is low 2 clocks later.
module tb; bit a, b; bit clk; // This is a sequence that says 'b' should be high 2 clocks after // 'a' is found high. The sequence is checked on every positive // edge of the clock which ultimately ends up having multiple // assertions running in parallel since they all span for more // than a single clock cycle. sequence s_ab; @(posedge clk) a ##2 b; endsequence // Print a display statement if the assertion passed assert property(s_ab) $display ("[%0t] Assertion passed !", $time); always #10 clk = ~clk; initial begin for (int i = 0; i < 10; i++) begin @(posedge clk); a <= $random; b <= $random; $display("[%0t] a=%b b=%b", $time, a, b); end #20 $finish; end endmodule
|Time (ns)||a||b||Sequence Start||Result|
|10||0||0||No||FAIL (Start@10, Fail@10)|
|30||0||1||No||FAIL (Start@30, Fail@30)|
|90||1||0||Yes||FAIL (Start@50, Fail@90)|
|110||1||1||Yes||PASS (Start@70, Pass@110)|
|130||0||1||No||PASS (Start@90, Pass@130)|
|150||1||0||Yes||FAIL (Start@110, Fail@150)|
|190||1||0||Yes||FAIL (Start@150, Fail@190)|
Compiler version P-2019.06-1; Runtime version P-2019.06-1; Jan 16 06:49 2020  a=0 b=0 "testbench.sv", 14: tb.unnamed$$_0: started at 10ns failed at 10ns Offending 'a'  a=0 b=1 "testbench.sv", 14: tb.unnamed$$_0: started at 30ns failed at 30ns Offending 'a'  a=1 b=1  a=1 b=1  a=1 b=0 "testbench.sv", 14: tb.unnamed$$_0: started at 50ns failed at 90ns Offending 'b'  a=1 b=1  Assertion passed !  a=0 b=1 "testbench.sv", 14: tb.unnamed$$_0: started at 130ns failed at 130ns Offending 'a'  Assertion passed !  a=1 b=0 "testbench.sv", 14: tb.unnamed$$_0: started at 110ns failed at 150ns Offending 'b'  a=1 b=0  a=1 b=0 "testbench.sv", 14: tb.unnamed$$_0: started at 150ns failed at 190ns Offending 'b' $finish called from file "testbench.sv", line 27. $finish at simulation time 210 V C S S i m u l a t i o n R e p o r t Time: 210 ns
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