What is virtual function?

In SystemVerilog, a virtual function is a type of function that allows a base class to define a function signature which can be overwritten in a derived class. This means that a virtual function can be customized by a subclass to perform a different function than the base class.

Virtual functions are an important aspect of object-oriented programming (OOP) and are used heavily in verification methodologies such as the Universal Verification Methodology (UVM). In UVM, virtual functions are used to customize the behavior of verification components and facilitate the reuse of code across different testbenches.

Read more on SystemVerilog Virtual Methods.

Difference between static and dynamic casting

Static and dynamic casting are type conversion operations used to convert between different data types.

Static casting is a compile-time operation in which the compiler converts a given data type into another data type. It is called static casting because the conversion is determined and enforced by the compiler at the time of compilation. Static casting is a simple and efficient process, but it can lead to errors or loss of information if the conversion is not compatible.

Dynamic casting, on the other hand, is a run-time operation in which the type of an object is determined at run-time and then explicitly converted to a different type. Dynamic casting is more complex and less efficient than static casting, but it is safer as it can detect and handle errors during runtime.

Read more on SystemVerilog Static Cast and Dynamic Cast.

Difference between virtual and pure virtual function

In Verilog and SystemVerilog, virtual and pure virtual functions are used in polymorphism and inheritance.

A virtual function is a function declared in a base class that can be overwritten in a derived class, enabling runtime polymorphism. When the function is called on an object of the derived class, the derived class's implementation of the function is executed. If there is no implementation in the derived class, the base class's implementation is executed. The syntax for a virtual function is declared by using the keyword virtual in the base class.

A pure virtual function, on the other hand, is a virtual function that has no implementation in the base class. This means that derived classes must provide an implementation for the function. If a derived class doesn't overwrite the pure virtual function, it will remain abstract and cannot be instantiated. Pure virtual functions are used to create abstract classes that act as a blueprint for derived classes.

virtual class BasePacket;
  pure virtual function int transfer(bit[31:0] data); // No implementation

class ExtPacket extends BasePacket;
  virtual function int transfer(bit[31:0] data);    

Why do we need randomization in SystemVerilog?

In SystemVerilog, randomization is the process of generating random stimuli or inputs to the design, which can help verify its functionality and reliability. Here are some reasons why we need randomization in SystemVerilog:

Read more on Constraint Random Verification.

Difference between while and do while.

In programming languages, the while loop and do-while loop are used for repetitive execution of a code block based on certain conditions. Here are the differences between while and do-while loops:

  1. Execution: In the while loop, the condition is checked first, and if it is true, then the code block is executed. However, in the do-while loop, the code block is executed first, and then the condition is checked. This means that the code block will be executed at least once in the do-while loop, even if the condition is initially false.
  2. Loop condition: In the while loop, the loop condition is checked at the beginning of each iteration. If the condition is false, the loop is terminated, and the control goes to the next statement after the loop. However, in the do-while loop, the loop condition is checked at the end of each iteration. This means that the code block is executed at least once, even if the condition is false.
  3. Initialization: In the while loop, the initialization of the loop variable or counter happens outside of the loop. This makes it possible to create an infinite loop if the initialization is incorrect. However, in the do-while loop the initialization of the loop variable or counter can be done within the loop.
  4. Use Cases: The while loop is used in cases where the condition is unknown, and the loop should not execute if the condition is false. In contrast, the do-while loop is used when we want the loop to execute at least once, even if the condition is false.

Read more on SystemVerilog while and do-while loop.

Explain bidirectional constraints

Bidirectional constraints are used to specify a relationship between two or more variables or signals, such that the value of one variable is dependent on the value of the other variable(s). In SystemVerilog, constraints are solved bidirectionally.

For example, if we have two signals, data_valid and data_ready we can specify the constraint that when data_valid is asserted data_ready must be asserted, using the following conditional constraint:

    data_valid -> data_ready;

Read more on SystemVerilog Implication Constraint.

Difference between integer and int

integer is a 4-state data type where as int is a 2-state data type. Both can hold 32-bit signed numbers.

Read more on SystemVerilog Data Types.

Write a constraint to have a variable divisible by 5.

To have a variable divisible by 5, we can use the following constraint:

constraint c_div5 { my_variable % 5 == 0; }

Here, the modulo operator % is used to retrieve the remainder of a division operation, and the constraint ensures that the remainder of the division of my_variable by 5 is equal to zero, which means my_variable is divisible by 5.

What are parameterized classes?

Parameterized classes in object-oriented programming (OOP) are classes that are defined with one or more parameters, allowing them to be customized or specialized during their instantiation or creation.

class stack #(type T = int);
  T item;             
  function T add_a (T a); 	
    return item + a;

Read more on SystemVerilog Parameterized Classes.

How can you establish communication between monitor and scoreboard in SystemVerilog?

In SystemVerilog, a monitor and scoreboard are typically used in a verification environment to check that a design is behaving correctly. The monitor observes the signals of the design and generates transactions, while the scoreboard compares these transactions against expected values and generates results, and they can be connected using a mailbox.

Read more on SystemVerilog Mailbox.