Processors, DMA engines, GPUs and memory controllers all want more bandwidth than a single pipelined bus can give. AXI is the AMBA answer: instead of one bus that every transfer must pass through in order, it splits each transaction across independent channels, lets a master keep many transactions in flight, and lets fast transactions overtake slow ones. This chapter explains AXI4 from its handshake to a complete memory slave.
The AXI protocol (Advanced eXtensible Interface) is the high-performance member of the AMBA family and the standard interface of most modern processor and memory IP. Where AHB moves one transfer per cycle through a single address and data pipeline, AXI uses five independent channels, sends only the start address of a burst, and allows many outstanding and out-of-order transactions. This article explains why those features exist and shows the effect of the most important one in a simulation.
8 min read | Intermediate
What You'll Learn
- Explain which limits of AHB AXI was designed to remove
- Name the five AXI channels and what each one carries
- Show how outstanding transactions hide memory latency
- List the differences between AXI3 and AXI4
What Limits AHB
AHB is fast for a bus that serves one master and quick slaves. Three things limit it in a larger system:
- One transfer at a time. The data phase of one transfer must finish before the next can finish. A slave with a long latency, such as a DRAM controller, holds the whole bus while it waits.
- Strict order. Transfers complete in the order they were issued, so a slow access delays every fast access behind it.
- A shared pipeline for reads and writes. A read and a write cannot move data in the same cycle.
The AXI Answer: Five Channels
AXI splits every transaction into parts that travel on separate channels:
| Channel | Direction | Carries |
|---|---|---|
| Write address (AW) | master to slave | Address and control of a write burst |
| Write data (W) | master to slave | Write data and byte strobes, one beat at a time |
| Write response (B) | slave to master | One response per write burst |
| Read address (AR) | master to slave | Address and control of a read burst |
| Read data (R) | slave to master | Read data and a response for every beat |
Every channel has its own VALID/READY handshake, the same one you met in Handshakes. Because the channels are independent, the specification lists these key features:
- separate address/control and data phases;
- burst-based transactions where only the start address is sent;
- separate read and write data channels, so a read and a write can move data at the same time;
- multiple outstanding addresses;
- out-of-order completion, using transaction IDs;
- unaligned transfers using byte strobes;
- easy insertion of register slices to meet timing, because every channel flows in one direction.
Quick Check
Q: A write burst of eight beats crosses the AXI interface. How many handshakes happen on the AW, W and B channels?
Show Answer
One on AW (the address and control of the whole burst), eight on W (one per beat), and one on B (one response for the whole burst).
Outstanding Transactions Hide Latency
A memory slave with a read latency of four cycles answers each read four cycles after it accepts the address. If the master waits for every read before sending the next address, each read costs the full latency. If it sends the next addresses while the first read is still in progress, the waits overlap.
The testbench in this chapter has a master with a command list per channel and a setting, max_reads, for how many read transactions it allows in flight. With one read in flight:
105 AR id=1 addr=0x000 len=0 size=4 INCR 145 R id=1 data=0x000000a0 OKAY last 155 AR id=1 addr=0x004 len=0 size=4 INCR 195 R id=1 data=0x000000a1 OKAY last 205 AR id=1 addr=0x008 len=0 size=4 INCR 245 R id=1 data=0x000000a2 OKAY last 255 AR id=1 addr=0x00c len=0 size=4 INCR 295 R id=1 data=0x000000a3 OKAY last
With up to four reads in flight, the same four reads:
105 AR id=1 addr=0x000 len=0 size=4 INCR 115 AR id=1 addr=0x004 len=0 size=4 INCR 125 AR id=1 addr=0x008 len=0 size=4 INCR 135 AR id=1 addr=0x00c len=0 size=4 INCR 145 R id=1 data=0x000000a0 OKAY last 155 R id=1 data=0x000000a1 OKAY last 165 R id=1 data=0x000000a2 OKAY last 175 R id=1 data=0x000000a3 OKAY last
Each read still takes four cycles from address to data, but the reads now overlap. The last data arrives at 175 ns instead of 295 ns. This is how a processor keeps a DRAM controller busy: it issues several cache line fills before the first one returns. The same idea was introduced in Pipelining and Outstanding Transactions; AXI builds it into the protocol.
Out-of-Order Completion
Outstanding transactions raise a question: what if the second read is to a fast memory and the first to a slow one? AXI lets each transaction carry an ID. Transactions with the same ID complete in order; transactions with different IDs may complete in any order. A fast read can then overtake a slow one, and the master matches the data to its request by ID. Transaction IDs and Ordering covers this in detail.
Quick Check
Q: With four reads in flight, did any single read get faster?
Show Answer
No. Each read still takes four cycles from its address to its data. What improved is the total time, because the four waits overlap instead of following each other.
AXI3 and AXI4
This chapter describes AXI4. Its main differences from AXI3 are:
- INCR bursts can be up to 256 beats long (AXI3: 16), so
AxLENis 8 bits wide. - Write data interleaving is gone, and with it the
WIDsignal: all beats of a write burst are consecutive on W. - Locked transactions are gone;
AxLOCKis one bit that selects an exclusive access. - New optional signals:
AxQOSfor quality of service,AxREGIONfor multiple logical interfaces, and user-definedxUSERsignals. - A slave must not give a write response before it has accepted the write address.
AXI4 also comes with two simpler relatives: AXI4-Lite for registers and AXI4-Stream for data without addresses, covered in the next chapter.
Running It in ChipVerify Lab
The example runs the four reads with up to four in flight. Change max_reads to 1 to see the difference.
Common Mistakes
Mistake #1: Treating AXI as a faster AHB
AXI has no address phase that lines up with a data phase. Address, data and response travel on independent channels with their own timing, and a design that assumes a fixed relation between them will break.
Mistake #2: Assuming responses come back in order
Only transactions with the same ID are ordered. A master that issues reads with different IDs must match the data by RID.
Mistake #3: Using AXI where AXI4-Lite or APB would do
A block with a few registers does not need bursts, IDs or outstanding transactions. Full AXI there only adds logic and verification work.
Practice Exercise
Challenge: A Slower Memory
Change the slave's READ_LAT parameter from 4 to 8 and run the four reads with one and with four in flight. How much time does each version take from the first address to the last data, and how much did outstanding reads save?
Hint
With one in flight, every read pays the full latency. With four in flight, the latency is paid about once.
Solution
One in flight: the first address is at 105 ns and the last data at 455 ns, 35 cycles. Four in flight: the last data arrives at 215 ns, 11 cycles. Outstanding reads saved 24 cycles here instead of 12 with a latency of 4: the longer the latency, the more there is to hide.
105 AR id=1 addr=0x000 len=0 size=4 INCR 115 AR id=1 addr=0x004 len=0 size=4 INCR 125 AR id=1 addr=0x008 len=0 size=4 INCR 135 AR id=1 addr=0x00c len=0 size=4 INCR 185 R id=1 data=0x000000a0 OKAY last 195 R id=1 data=0x000000a1 OKAY last 205 R id=1 data=0x000000a2 OKAY last 215 R id=1 data=0x000000a3 OKAY last
Open the ready-made example in the lab and run the simulation.
Summary
- AXI splits each transaction across five independent channels: AW, W, B, AR and R.
- Only the start address of a burst is sent; the slave calculates the rest.
- Multiple outstanding transactions overlap the latency of slow slaves.
- Transaction IDs allow out-of-order completion between different IDs.
- AXI4 extends INCR bursts to 256 beats and drops write interleaving and locked transactions.
