Interconnects and Address Maps in an AMBA SoC

The interconnect is the part of an AMBA system that every transaction passes through. It decodes each address to find the slave, arbitrates when several masters want the same slave, extends transaction IDs so that responses find their way back, and sends anything that matches no slave to a default slave. All of this is driven by one table: the address map. This article explains both, and builds a small AXI4-Lite interconnect with two slaves and a default slave.

9 min read | Intermediate

What You'll Learn

• Read and design an SoC address map
• List the jobs of an AXI interconnect
• Explain DECERR and the default slave
• Follow transactions through a simple AXI4-Lite interconnect

An AMBA SoC

Two processors and a DMA engine are AXI masters. The AXI interconnect connects them to the DDR controller, an on-chip SRAM, a boot ROM, and an AXI-to-APB bridge for the peripherals. Every one of those slaves owns one or more address ranges, and those ranges together form the address map.

Rules for a Good Address Map

• Align regions to their size. A 64 KB region starts on a 64 KB boundary, so the decoder compares only the upper address bits.
• Use at least 4 KB per AXI slave. AXI bursts never cross a 4 KB boundary, so a slave that owns whole 4 KB pages never sees half a burst. AHB uses 1 KB for the same reason.
• Give each APB peripheral its own 4 KB page. It costs nothing in a 32-bit address space and lets memory management units protect each peripheral separately.
• Leave gaps on purpose. Unused space goes to the default slave, which turns a wild pointer into a clean error instead of a hang.
• Keep the boot ROM where the processor starts. The reset address of the processor fixes the location of the first code it runs.

What an Interconnect Does

• Decode: look at AWADDR and ARADDR and pick the slave.
• Arbitrate: when several masters target the same slave, choose who goes next. AXI has no arbitration signals; this happens inside the interconnect, per slave.
• Extend IDs: append the master port number to AWID and ARID on the way to the slave, and use it to route BID and RID back, as described in Transaction IDs and Ordering.
• Keep order where needed: make sure that responses with the same ID from different slaves reach the master in order.
• Convert: adapt data widths, clocks, AXI4 to AXI4-Lite, or AXI to APB on some ports.
• Answer the gaps: route unmapped addresses to a default slave that returns DECERR and completes every beat.

The AXI specification describes three common structures: a shared address and data bus, a shared address bus with several data buses, and a full multilayer crossbar. Because data bandwidth is usually the limit, the middle option is a popular compromise.

A Small AXI4-Lite Interconnect

The example interconnect has one master port and two slave ports, with this map:

The decoder is one function on the top address bits:

function [1:0] decode(input [11:0] a);
  decode = (a[11:10] == 2'b00) ? 2'd0 : (a[11:10] == 2'b01) ? 2'd1 : 2'd2;
endfunction

On the write side, the interconnect takes the address, decodes it, and forwards it; it takes the write data only once it knows the destination; and it registers the slave's response before passing it back. For the default slave it simply answers DECERR once the data has arrived:

if (w_have && (w_sel == 2'd2 || M_WREADY[w_sel])) begin
  w_have <= 1'b0;
  w_sent <= 1'b1;
  if (w_sel == 2'd2) begin
    b_have <= 1'b1;                // the default slave answers once it has the data
    b_resp <= DECERR;
  end
end
if (w_sel != 2'd2 && w_busy && !b_have && M_BVALID[w_sel]) begin
  b_have <= 1'b1;                  // take the slave's response
  b_resp <= (w_sel == 2'd1) ? M_BRESP[3:2] : M_BRESP[1:0];
end

Every signal the interconnect drives comes from a register, so there is no combinational path from a slave's outputs to the master's inputs or back. The price is latency: each transaction passes through a few register stages.

The Simulation

The master writes the CTRL register of each slave, writes to an unmapped address, then reads back:

35  AW  id=0 addr=0x000 len=0 size=4 INCR
45  W   data=0x00000a00 strb=1111 last
85  B   id=0 OKAY
95  AW  id=0 addr=0x400 len=0 size=4 INCR
105  W   data=0x00000b00 strb=1111 last
145  B   id=0 OKAY
155  AW  id=0 addr=0x800 len=0 size=4 INCR
165  W   data=0x00000c00 strb=1111 last
185  B   id=0 DECERR
195  AR  id=0 addr=0x000 len=0 size=4 INCR
225  R   id=0 data=0x00000a00 OKAY last
235  AR  id=0 addr=0x400 len=0 size=4 INCR
265  R   id=0 data=0x00000b00 OKAY last
275  AR  id=0 addr=0x40c len=0 size=4 INCR
305  R   id=0 data=0x41584c31 OKAY last
315  AR  id=0 addr=0x408 len=0 size=4 INCR
345  R   id=0 data=0x00000001 OKAY last
355  AR  id=0 addr=0xc00 len=0 size=4 INCR
375  R   id=0 data=0x00000000 DECERR last

The two slaves hold different CTRL values (0xA00 and 0xB00), which shows the routing worked, and slave 1's COUNT is 1 because only one write reached it. The writes and reads to 0x800 and 0xC00 reached the default slave and got DECERR. Note that slave 1 received address 0x00C for the read of 0x40C: the interconnect removes the region bits, and the slave decodes only the low bits.

Running It in ChipVerify Lab

The example contains the interconnect, two register slaves and the testbench. Add accesses to other addresses and predict which slave answers.

Common Mistakes

315  AR  id=0 addr=0x7fc len=0 size=4 INCR
345  R   id=0 data=0x00000000 SLVERR last