I2C (Inter-Integrated Circuit) connects many low-speed devices with just two wires: a clock, SCL, and a data line, SDA. Every device has an address, so one controller can talk to dozens of sensors, EEPROMs and power-management chips without a chip select per device. The price is speed and a little subtlety: the lines are open drain, and the protocol uses special conditions on SDA to mark the start and end of each transaction. This article explains the bus, START and STOP, addressing and acknowledgement, with a simulated transaction.
9 min read | Beginner to Intermediate
What You'll Learn
- Explain why I2C uses open-drain lines with pull-up resistors
- Recognize START, STOP and valid data bits on SDA and SCL
- Decode the address byte and the R/W bit
- Use ACK and NACK to follow a transaction
Two Open-Drain Lines
Both SCL and SDA are connected to the supply through pull-up resistors. Every device's outputs are open drain: they can pull a line low or let it go, but never drive it high. When nobody pulls, the resistor makes the line high. This is a wired-AND: the line is high only if every device releases it. Two consequences make I2C work:
- several devices can share the lines without ever fighting, because a device driving high does not exist;
- any device can hold a line low to make the others wait, which enables clock stretching and arbitration.
The specification defines several speeds: up to 100 kbit/s in Standard-mode, 400 kbit/s in Fast-mode, 1 Mbit/s in Fast-mode Plus and 3.4 Mbit/s in High-speed mode. The rise time through the pull-up resistor and the bus capacitance limits how fast and how long a bus can be.
The current I2C specification calls the device that drives the clock and starts transactions the controller, and a device that responds to its address a target. Older documents say master and slave.
START, STOP and Data Bits
- Data: SDA may only change while SCL is low. While SCL is high, SDA must be stable; that is when the bit is read.
- START (S): SDA goes from high to low while SCL is high. It begins every transaction.
- STOP (P): SDA goes from low to high while SCL is high. It ends the transaction and frees the bus.
Because data never changes while SCL is high, a change of SDA during SCL high can only be START or STOP. Every device recognizes them, no matter where in a byte they occur, and resets its bus logic on a START.
Quick Check
Q: A target sees SDA fall while SCL is high, in the middle of a data byte. What does it do?
Show Answer
It treats it as a START condition, abandons the byte in progress, and expects an address byte next. Devices must reset their bus logic on any START, even an unexpected one.
Bytes, Addresses and ACK
Everything on SDA is sent in bytes, most significant bit first, and every byte is followed by a ninth clock for the acknowledge:
- ACK: the receiver pulls SDA low during the ninth clock: "received, send more".
- NACK: SDA stays high: nobody answered, the receiver cannot take more, or a controller reading data signals the last byte.
The first byte after START is the address byte: a 7-bit target address and an R/W bit, 0 for write and 1 for read. Only the target whose address matches acknowledges it. 10-bit addresses also exist, using reserved address patterns, but are rarely used.
A Register Write
Most I2C devices hold registers behind a pointer: the controller writes the register number, then data. The example has a controller and two targets at 0x50 and 0x51, each with four registers. Writing 0xA7 to register 1 of target 0x50 is: S, 0x50 + W, ACK, 0x01, ACK, 0xA7, ACK, P.
6015 write 0x50 reg1 = 0xa7 11965 write 0x51 reg1 = 0x3c 19975 read 0x50 reg1 = 0xa7 27985 read 0x51 reg1 = 0x3c 30275 write 0x52: no ACK (NACK)
The address byte 0xA0 (0x50 shifted left with W = 0) is acknowledged only by target 0x50; target 0x51 sees the same bits and stays silent. The last write goes to 0x52, where there is no device: nobody pulls SDA low in the ninth clock, the controller reads a NACK, and it ends the transaction with STOP. The SCL clock in the simulation runs at 5 MHz to keep the waveforms short; real buses use 100 kHz to 1 MHz.
Quick Check
Q: What is the address byte for a read from target 0x68?
Show Answer
0x68 shifted left by one with R/W = 1: 0xD1. Datasheets sometimes give the 8-bit form (0xD0 for write, 0xD1 for read) instead of the 7-bit address 0x68, a common source of confusion.
Running It in ChipVerify Lab
The example contains the I2C controller, two targets and the testbench. Find the START, the address byte and each ACK in the waveform.
Common Mistakes
Mistake #1: No pull-up resistors
Open-drain outputs cannot drive high. Without pull-ups the lines never rise and nothing works; with resistors that are too large, the edges are too slow for the chosen speed.
Mistake #2: Mixing 7-bit and 8-bit address notation
A datasheet address of 0xA0 may be the 8-bit write address of 7-bit address 0x50. Check which form a driver expects.
Mistake #3: Driving SDA high
A push-pull output on SDA fights any device that pulls low, and breaks ACK, clock stretching and arbitration. Always release the line instead.
Practice Exercise
Challenge: A Missing Device
Change the address of the second target from 0x51 to 0x52. Predict what the writes and reads to 0x51 and 0x52 do now, then run it.
Hint
A target only acknowledges its own address. What does SDA read as when nobody drives it?
Solution
6015 write 0x50 reg1 = 0xa7 8305 write 0x51: no ACK (NACK) 16315 read 0x50 reg1 = 0xa7 24325 read 0x51 reg1 = 0xff 30275 write 0x52 reg0 = 0x00
The write to 0x51 gets a NACK and stops after the address byte. The read of 0x51 returns 0xFF: with no target driving SDA, the pull-up makes every bit 1. A real driver would check the ACK of the address byte before trusting the data. The write to 0x52 now succeeds.
Open the ready-made example in the lab and run the simulation.
Summary
- I2C uses two open-drain lines, SCL and SDA, with pull-up resistors: a wired-AND bus.
- SDA changes only while SCL is low, except for START (SDA falls, SCL high) and STOP (SDA rises, SCL high).
- Bytes are MSB first, each followed by an ACK (SDA low) or NACK (SDA high) in the ninth clock.
- The first byte is a 7-bit target address plus R/W; only the matching target acknowledges.
- Speeds range from 100 kbit/s to 3.4 Mbit/s; the specification names the roles controller and target.
