Interconnects: Shared Bus, Crossbar and Network-on-Chip

An interconnect is the part of a chip that connects all masters to all slaves. Its structure decides how much traffic can flow at once. A shared bus lets one transfer through at a time, a crossbar lets every slave serve a different master in parallel, and a network-on-chip sends packets through routers like a small internet. This article compares the three, and measures the difference between a shared bus and a crossbar in a simulation.

8 min read | Intermediate

What You'll Learn

• Describe shared-bus, crossbar and network-on-chip interconnects
• Explain why a crossbar raises bandwidth, and when it does not
• Measure shared bus against crossbar in a simulation
• Know which interconnects AHB and AXI systems use

Three Topologies

• Shared bus: one set of wires that all masters and slaves use in turn. An arbiter grants it to one master at a time. Cheap and simple, but the total bandwidth is one transfer per cycle, however many slaves there are. Classic AHB systems are built this way.
• Crossbar: every master has a path to every slave. Each slave has its own arbiter, so two masters can talk to two different slaves in the same cycle. AHB multi-layer systems and AXI interconnects are crossbars. Their cost grows with masters times slaves.
• Network-on-chip (NoC): transfers become packets that travel through routers connected by links. It scales to dozens of masters and slaves, and large SoCs use it for the main interconnect, with AXI interfaces at its edges.

Shared Bus Against Crossbar

The model has two masters and two slaves. Each master wants four single-cycle transfers. The interconnect grants requests every cycle; the only difference is what counts as a conflict:

wire conflict = CROSSBAR ? (req == 2'b11 && tgt0 == tgt1)   // same slave
                         : (req == 2'b11);                   // one shared bus

always @(*) begin
  if (conflict)
    gnt = last ? 2'b01 : 2'b10;
  else
    gnt = req;
end

On a shared bus, any two requests conflict. In a crossbar, two requests only conflict when they go to the same slave. In the first test, master 0 talks to slave 0 and master 1 to slave 1:

shared bus: 8 transfers took 8 cycles
crossbar:   8 transfers took 4 cycles

When a Crossbar Does Not Help

A crossbar only adds bandwidth when masters use different slaves. If both masters target the same slave, they conflict exactly as on a shared bus, and the eight transfers take eight cycles again. In real systems, most traffic goes to one place, the DRAM controller, so that slave becomes the bottleneck no matter how the interconnect is built. That is why memory controllers have several ports and deep queues, and why caches matter so much.

Interconnects in AMBA Systems

• An AHB system with one master needs only a decoder and a multiplexer; with several masters, an arbiter, or a multi-layer interconnect with one layer per master.
• An AXI interconnect is usually a crossbar, with arbitration per slave, address decoding per master, and often width conversion, clock conversion and buffering built in.
• APB is always behind a bridge, so the APB side has a single master, the bridge, and needs no arbitration at all.

Running It in ChipVerify Lab

The example contains both interconnects and the testbench. Run it, then try the exercise to see the crossbar lose its advantage.

Common Mistakes