AXI Write Transactions: AW, W and B

An AXI write transaction uses three channels: the master sends the address and burst description on AW, the data beats on W, and the slave confirms the whole burst with a single response on B. This article walks through each channel's signals, follows two write bursts through a simulation, and explains when a write counts as complete.

8 min read | Intermediate

What You'll Learn

• Describe the signals of the AW, W and B channels
• Explain how AWLEN and WLAST define the burst
• Match a write response to its transaction with BID
• Know when a master may treat a write as finished

The Write Address Channel (AW)

One AW handshake describes the whole burst:

Only the start address is sent. The slave calculates the address of every following beat from AWSIZE and AWBURST, as described in AXI Burst Types.

The Write Data Channel (W)

Each W handshake moves one beat: WDATA, a byte strobe WSTRB with one bit per byte lane, and WLAST, which the master must assert on the final beat. AXI4 has no WID: the beats of one burst are always consecutive on W, and bursts arrive in the same order as their addresses. The master may still pause between beats by lowering WVALID.

The Write Response Channel (B)

After the last beat, the slave sends one response for the whole burst: BID repeats the AWID, and BRESP is OKAY, EXOKAY, SLVERR or DECERR. Every write transaction gets exactly one response, never one per beat.

Two Writes in a Simulation

The master writes four words with ID 1 to 0x100, then two words with ID 2 to 0x200. It pauses for two cycles before the last beat of the second burst. Both are then read back.

write(1, 12'h100, 3, WORD, INCR, 32'h10, 0, 0, 0);   // INCR, 4 beats, ID 1
write(2, 12'h200, 1, WORD, INCR, 32'h20, 0, 0, 0);   // INCR, 2 beats, ID 2
w_delay[5] = 2;                                      // the master pauses before the last beat

35  AW  id=1 addr=0x100 len=3 size=4 INCR
45  W   data=0x00000010 strb=1111
55  W   data=0x00000011 strb=1111
65  W   data=0x00000012 strb=1111
75  W   data=0x00000013 strb=1111 last
85  B   id=1 OKAY
95  AW  id=2 addr=0x200 len=1 size=4 INCR
105  W   data=0x00000020 strb=1111
135  W   data=0x00000021 strb=1111 last
145  B   id=2 OKAY

Several things are visible in the waveform:

• The master raises AWVALID for the second burst straight after the first address. It waits, with AWVALID high, until the slave can take it: this slave handles one write at a time.
• The master's write data for both bursts is ready early; WVALID waits for WREADY.
• The gap before the last beat of ID 2 simply delays WLAST and the response.
• Each burst gets one B handshake, carrying its own ID.

Inside the Slave

The memory slave's write side registers the burst description on AW, then handles one beat per W handshake and raises BVALID on the last one:

if (AWVALID && AWREADY) begin
  w_active <= 1'b1;
  w_id     <= AWID;
  w_addr   <= AWADDR;
  // ... AWLEN, AWSIZE, AWBURST, AWLOCK
end
if (WVALID && WREADY) begin
  // write the bytes enabled by WSTRB at w_addr ...
  w_addr <= next_addr(w_addr, w_size, w_burst, w_len);
  if (WLAST) begin
    w_active <= 1'b0;
    BVALID   <= 1'b1;
    BID      <= w_id;
    // BRESP: OKAY, EXOKAY or SLVERR
  end
end

With AWREADY = !w_active && !BVALID and WREADY = w_active, the response can never come before the address, as AXI4 requires. Designing an AXI4 Memory Slave shows the complete design.

When Is a Write Complete?

Sending the last data beat does not finish a write. The master may only treat a write as complete when it receives the write response. This matters when a later transaction depends on it, such as a read of the same address or a write to a peripheral's "go" register after its configuration. AXI does not order reads against writes, even with the same ID, so the master must wait for B before it issues the dependent transaction.

Running It in ChipVerify Lab

The example runs these two writes and reads them back. Look at how long AWVALID waits for the second burst.

Common Mistakes

35  AW  id=1 addr=0x100 len=3 size=4 INCR
45  W   data=0x00000010 strb=1111
55  W   data=0x00000011 strb=1111
65  W   data=0x00000012 strb=1111
75  W   data=0x00000013 strb=1111 last
135  B   id=1 OKAY
145  AW  id=2 addr=0x200 len=1 size=4 INCR
155  W   data=0x00000020 strb=1111
185  W   data=0x00000021 strb=1111 last
195  B   id=2 OKAY