AXI moves data in byte lanes. A 32-bit data bus has four lanes, and every write beat carries a strobe, WSTRB, with one bit per lane that says which bytes are valid. Strobes make three things possible: narrow transfers that use only part of the bus, unaligned bursts that start in the middle of a word, and sparse writes that skip bytes. This article shows all three, with the byte lanes taken from a simulation.
8 min read | Intermediate
What You'll Learn
- Map
WSTRBbits to byte lanes ofWDATA - Work out the byte lanes of narrow transfers in a burst
- Describe an unaligned burst and its first beat
- Write memory correctly from the strobes in a slave
Write Strobes
WSTRB[n] covers WDATA[8n+7:8n]. A slave writes only the bytes whose strobe is high, so the master can update single bytes without disturbing their neighbours. The master must keep the strobes high only for lanes that carry valid data. While WVALID is low the strobes may take any value, though the specification recommends driving them low or holding them.
Read data has no strobes. For a narrow or unaligned read, the slave drives the whole bus and the master picks out the bytes it asked for.
Narrow Transfers
When the beat size (AxSIZE) is smaller than the bus, the address decides which lanes each beat uses. In an INCR or WRAP burst the lanes move with the address from beat to beat; in a FIXED burst they stay the same.
For example, an INCR burst of five bytes from address 0 on a 32-bit bus uses lane 0, then 1, 2, 3, and lane 0 again for address 4. The first part of the simulation writes exactly this burst, with every byte carrying the low 8 bits of its own address:
45 slave: write beat at 0x000, WSTRB 0001 55 slave: write beat at 0x001, WSTRB 0010 65 slave: write beat at 0x002, WSTRB 0100 75 slave: write beat at 0x003, WSTRB 1000 85 slave: write beat at 0x004, WSTRB 0001
Unaligned Transfers
A burst of words does not have to start on a word boundary. A master can signal an unaligned start in two ways: with the low address bits (start address 0x101) or with an aligned address and strobes that leave out the first bytes. The address and the strobes must agree. In both cases only the first beat is unaligned; every following beat is aligned, because the address increments from the aligned address.
The second part of the simulation writes four words starting at 0x101:
115 slave: write beat at 0x101, WSTRB 1110 125 slave: write beat at 0x104, WSTRB 1111 135 slave: write beat at 0x108, WSTRB 1111 145 slave: write beat at 0x10c, WSTRB 1111
The first beat covers bytes 0x101 to 0x103 only (lanes 1 to 3). The burst therefore moves 15 bytes, not 16: the unaligned start costs one byte of the first beat. Reading the words back shows every byte where it belongs:
355 R id=1 data=0x03020100 OKAY 365 R id=1 data=0x00000004 OKAY last 375 R id=1 data=0x03020100 OKAY 385 R id=1 data=0x07060504 OKAY 395 R id=1 data=0x0b0a0908 OKAY 405 R id=1 data=0x0f0e0d0c OKAY last
Byte 0x100 was never written: the lowest byte of the word at 0x100 is still the memory's initial 0x00. It only looks like part of the pattern because the pattern value for that byte would also have been 0x00.
Quick Check
Q: A master writes an INCR burst of two words starting at 0x1006 on a 32-bit bus. What are the beat addresses and the strobes?
Show Answer
Beat 1 at 0x1006 with WSTRB = 1100 (bytes 0x1006 and 0x1007). Beat 2 at 0x1008, aligned, with WSTRB = 1111.
Generating the Strobes
The testbench master computes the lanes of each beat with the same equations as the specification: the lowest lane is the address modulo the bus width, and the highest lane is the end of the aligned beat:
for (k = 0; k <= len; k = k + 1) begin
lo = a[1:0]; // lowest byte lane of this beat
hi = ((a & ~(bytes - 12'd1)) + bytes - 12'd1) & 12'd3; // highest byte lane
w_strb[wn] = 4'b0000;
for (b = 0; b < 4; b = b + 1) begin
if (b >= lo && b <= hi)
w_strb[wn][b] = 1'b1;
end
// ... data and WLAST ...
a = next_addr(a, size, burst, len);
end
The slave side is simpler: it does not need to know about alignment at all. It writes the bytes whose strobes are high into the word at the beat address:
if (WSTRB[0])
mem[w_addr[11:2]][7:0] <= WDATA[7:0];
if (WSTRB[1])
mem[w_addr[11:2]][15:8] <= WDATA[15:8];
if (WSTRB[2])
mem[w_addr[11:2]][23:16] <= WDATA[23:16];
if (WSTRB[3])
mem[w_addr[11:2]][31:24] <= WDATA[31:24];
Sparse Writes and Byte Invariance
Strobes do not have to be contiguous. A master may write bytes 0 and 2 of a word with WSTRB = 0101, and it may even drive all strobes low on the remaining beats of a burst it wants to stop early, since bursts cannot be cut short.
AXI is byte-invariant: a byte at a given address always travels on the same lane, whether the data structure around it is little-endian or big-endian. That is what lets big-endian and little-endian data share one memory without corrupting each other.
Quick Check
Q: Why can a write-only master stop a burst early with strobes, but a read master cannot do the same?
Show Answer
A write beat with all strobes low writes nothing, so the remaining beats are harmless. A read has no strobes: the slave reads every beat, which matters for read-sensitive devices such as FIFOs. The read master must request the right length in the first place.
Running It in ChipVerify Lab
The example writes the narrow and the unaligned burst with the slave trace on and reads them back.
Common Mistakes
Mistake #1: All strobes high on a narrow transfer
A byte write with WSTRB = 1111 overwrites three neighbouring bytes with whatever is on the unused lanes.
Mistake #2: Address and strobes that disagree
For an unaligned start, the low address bits and the strobes must describe the same bytes. A slave that uses only the strobes and one that uses only the address must both get the same result.
Mistake #3: Putting narrow data on lane 0
Data for address 0x003 travels on lane 3. A master that always puts narrow data in the low bits writes the wrong byte.
Practice Exercise
Challenge: Unaligned Halfwords
Replace the unaligned word burst with an INCR burst of three halfwords starting at 0x203. Predict the beat addresses and the strobes, then run it.
Hint
The first beat ends at the end of its aligned halfword, 0x203. After that, beats are aligned halfwords.
Solution
write(1, 12'h203, 2, HALF, INCR, 0, 1, 0, 0); // 3 halfwords from 0x203
115 slave: write beat at 0x203, WSTRB 1000 125 slave: write beat at 0x204, WSTRB 0011 135 slave: write beat at 0x206, WSTRB 1100
The first beat carries a single byte, 0x203, on lane 3. The next beats are aligned halfwords at 0x204 (lanes 1 and 0) and 0x206 (lanes 3 and 2): five bytes in total.
Open the ready-made example in the lab and run the simulation.
Summary
WSTRBhas one bit per byte lane; the slave writes only the enabled bytes.- Narrow beats move across the lanes with the address in INCR and WRAP bursts, and stay put in FIXED bursts.
- Only the first beat of an unaligned burst is unaligned; the rest start from the aligned address.
- A slave can write memory from the strobes alone, without decoding alignment.
- AXI is byte-invariant: a byte always uses the lane given by its address.
