AHB Wait States and Error Responses

Once a master has started an AHB transfer, the slave decides how it ends. It can finish at once, insert wait states with HREADYOUT, or fail the transfer with an ERROR response. Because AHB is pipelined, each of these also affects the transfer behind it, and the ERROR response takes two cycles for exactly that reason. This article explains the three outcomes and what the master may and may not change while it waits.

9 min read | Intermediate

What You'll Learn

• Combine HRESP and HREADY into the three possible slave responses
• Insert wait states and know what the master must hold meanwhile
• Explain why an ERROR response takes two cycles
• Cancel the rest of a burst after an error

Three Ways a Transfer Can End

The complete response is a combination of HRESP and HREADYOUT (which the master sees as HREADY):

A master cannot cancel a transfer once it has started; the slave always gets to finish it. Every slave must also answer IDLE and BUSY transfers with OKAY and no wait states, since there is nothing to do for them.

Wait States

A slave that needs time holds HREADYOUT low in the data phase and keeps HRESP at OKAY. Each such cycle is a wait state. While HREADY is low:

• the master holds HWDATA for a write;
• the slave only has to drive valid HRDATA in the final cycle of a read;
• the next transfer's address phase is held too.

The specification recommends that a slave inserts no more than 16 wait states, so that one access cannot lock the bus for long, and that every slave has a known maximum. A boot ROM read only at startup is the usual exception.

Here the memory slave inserts two wait states on the first beat of a read burst and one on each following beat. Writes are buffered and never wait. The burst before it is an INCR4 write with a BUSY cycle:

35  write 0x0010 = 0x000000a0  OKAY
55  write 0x0014 = 0x000000a1  OKAY
65  write 0x0018 = 0x000000a2  OKAY
75  write 0x001c = 0x000000a3  OKAY
105  read  0x0010 = 0x000000a0  OKAY
125  read  0x0014 = 0x000000a1  OKAY
145  read  0x0018 = 0x000000a2  OKAY
165  read  0x001c = 0x000000a3  OKAY

The read burst starts straight after the last write beat, and each waited beat holds the next address on HADDR: 0x14 stays for three cycles while the first beat waits twice. The four reads take 90 ns instead of 40 ns.

What the Master May Change During a Wait

Normally the master holds its address phase while HREADY is low. The specification allows a few changes:

• IDLE to NONSEQ: a master showing IDLE may change its mind and start a transfer. Once it shows NONSEQ, it must hold it until HREADY is high. The address of an IDLE transfer may also change during the wait.
• BUSY to SEQ: in a fixed-length burst, a master showing BUSY may switch to SEQ, and must then hold it.
• BUSY to anything: in an INCR burst, a master showing BUSY may switch to SEQ to continue, or to IDLE or NONSEQ to end the burst.
• After an ERROR: the master may change the address and switch to IDLE.

Everything else, including an address or a NONSEQ/SEQ type, stays put until HREADY is high.

The Two-Cycle ERROR Response

Why two cycles? By the time a slave decides a transfer has failed, the master has already put the next address on the bus. If that next transfer is the following beat of a burst, the master may not want it to happen. The first ERROR cycle, with HREADY low, freezes the pipeline and tells the master; in the second cycle, the master can replace the pending transfer with IDLE before it is accepted.

The memory slave reports ERROR for any write to its read-only region at 0x300 and above. This INCR4 write starts at 0x2F8, so its third beat lands at 0x300:

45  write 0x02f8 = 0x000000c0  OKAY
55  write 0x02fc = 0x000000c1  OKAY
75  write 0x0300 = 0x000000c2  ERROR
105  read  0x02f8 = 0x000000c0  OKAY
125  read  0x02fc = 0x000000c1  OKAY

The beat to 0x300 takes two cycles, both with HRESP high. The master sees the first cycle (ERROR with HREADY low) and drives HTRANS = IDLE in the second cycle instead of SEQ, so the beat to 0x304 never happens. Cancelling is the master's choice: the specification also allows it to continue the burst, and it does not have to repeat the missing beats later.

In the slave, the ERROR response is two flags:

wire start = HREADY && HSEL && HTRANS[1];        // NONSEQ or SEQ accepted
wire bad   = start && HWRITE && (HADDR[9:0] >= RO_BASE);

always @(posedge HCLK) begin
  // ... reset and the normal address-phase capture ...
  err2 <= err1;                          // second cycle follows the first
  if (err1)
    err1 <= 1'b0;
  else if (HREADY)
    err1 <= bad;                         // first cycle starts in the data phase
end

assign HREADYOUT = err1 ? 1'b0 : (wait_left == 4'd0);
assign HRESP     = err1 || err2;

A slave that needs more time to discover the error can insert ordinary wait states first, with HRESP at OKAY, and then give the two ERROR cycles. For a read that ends with ERROR, the read data does not have to be valid.

Running It in ChipVerify Lab

The example runs the INCR4 write into the read-only region and the reads that follow. Find the two ERROR cycles and the IDLE that replaces the last beat.

Common Mistakes

45  write 0x02f8 = 0x000000c0  OKAY
55  write 0x02fc = 0x000000c1  OKAY
75  write 0x0300 = 0x000000c2  ERROR
95  write 0x0304 = 0x000000c3  ERROR
115  read  0x02f8 = 0x000000c0  OKAY
135  read  0x02fc = 0x000000c1  OKAY