Bridges and Clock Domain Crossing

A chip rarely has one bus. A fast interconnect serves the processor and memory, a slow peripheral bus serves the UARTs and timers, and the two often run on different clocks. A bridge connects two buses: it accepts transfers on one side and repeats them on the other, converting the protocol and, if needed, the clock. This article explains what bridges do and shows the hardest part of their job, passing data safely between two clock domains, with a handshake simulated across a 10 ns and a 14 ns clock.

10 min read | Intermediate

What You'll Learn

• Describe what a bus bridge does
• Explain why signals between clock domains need synchronizers
• Pass a data word across clock domains with a four-phase handshake
• Know when an asynchronous FIFO is the better choice

What a Bridge Does

A bridge is a slave on one bus and a master on the other. An AXI-to-APB bridge, for example, is an AXI slave on the fast interconnect; for every AXI transfer to a peripheral address, it runs an APB transfer as the APB master, waits for the peripheral, and returns the response on AXI. On the way it converts:

• Protocol: AXI's channels and IDs become APB's simple two-phase transfers.
• Width: a 64-bit bus to a 32-bit bus, splitting wide transfers.
• Bursts: APB has no bursts, so each beat becomes its own APB transfer.
• Clock: the peripheral bus often runs slower, or from a different clock source.

The chip overview in the first article shows where the bridge sits. The AMBA chapters return to concrete bridges.

The Clock Domain Problem

Inside one clock domain, every flip-flop samples its input at the same clock edge, and static timing analysis guarantees the input is stable then. Between two unrelated clocks, nothing guarantees that. A signal from domain A can change just as a flip-flop in domain B samples it. The flip-flop can then go metastable: its output hovers between 0 and 1 for an unpredictable time before settling. Two rules handle this:

• Single control bits pass through a synchronizer: two flip-flops in a row in the receiving domain. The first may go metastable; the second almost always sees a settled value.
• Multi-bit data must never go through separate synchronizers, because the bits may settle in different cycles and form a word that never existed. Instead, the data is held steady while a single control bit, synchronized, says it is ready.

A Handshake Across Two Clocks

The four-phase handshake from the handshakes article is made for this. The sender in domain A puts the word on data and raises req. req crosses into domain B through a synchronizer; the receiver samples data, which has been stable for at least two clk_b cycles by then, and raises ack. ack crosses back into domain A through another synchronizer, and both sides return to zero.

module sync2 (
  input      clk,
  input      rst,
  input      d,
  output reg q
);
  reg meta;                        // first stage: may go metastable in real silicon

  always @(posedge clk) begin
    if (rst) begin
      meta <= 1'b0;
      q    <= 1'b0;
    end
    else begin
      meta <= d;
      q    <= meta;
    end
  end
endmodule

The sender only starts a new word when both req and the synchronized ack are low, so data never changes while the receiver might be sampling it. Domain A runs at 10 ns, domain B at 14 ns, and three words cross:

30  domain A sends    c0
91  domain B received c0
170  domain A sends    c1
231  domain B received c1
310  domain A sends    c2
371  domain B received c2

Each word takes 140 ns, fourteen clk_a cycles, from send to the end of the four phases: two synchronizer stages in each direction, twice. A simulation cannot show metastability, because simulated flip-flops always settle at once; the synchronizers are there for silicon. What the simulation does show is the protocol: the data is stable whenever domain B samples it.

Handshake or Asynchronous FIFO?

Bridges to peripheral buses usually use a handshake, because register accesses are rare. Clock converters on AXI data paths use asynchronous FIFOs.

Running It in ChipVerify Lab

The example contains the sender, receiver and synchronizers, with two clocks of 10 ns and 14 ns. Run it and follow req and ack across the two domains in the waveform.

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