Handshakes: Req/Ack and Valid/Ready

Whenever two blocks exchange data, each side must know when the other is ready. A handshake is the small protocol that settles this: the sender says "here is data", the receiver says "I have it". Every bus in this tutorial is built on one of three handshakes: four-phase request/acknowledge, two-phase request/acknowledge, and valid/ready. This article simulates all three side by side and shows why modern buses use valid/ready.

9 min read | Beginner

What You'll Learn

• Describe four-phase and two-phase request/acknowledge handshakes
• Describe the valid/ready handshake and its two rules
• Compare the throughput of the three handshakes
• Implement each handshake in Verilog

Four-Phase Request/Acknowledge

The oldest and most robust handshake has four steps, called phases:

1. The sender puts the data on the bus and raises req.
2. The receiver takes the data and raises ack.
3. The sender sees ack and lowers req.
4. The receiver sees req low and lowers ack. Both are back at zero, ready for the next word.

module hs4_sender (
  input            clk,
  input            rst,
  input            go,
  input      [7:0] din,
  input            ack,
  output reg       req,
  output reg [7:0] data
);
  always @(posedge clk) begin
    if (rst) begin
      req <= 1'b0;
    end
    else if (go && !req && !ack) begin     // phase 1: request, with the data
      req  <= 1'b1;
      data <= din;
    end
    else if (req && ack) begin             // phase 3: drop the request
      req <= 1'b0;
    end
  end
endmodule

module hs4_receiver (
  input            clk,
  input            rst,
  input            req,
  input      [7:0] data,
  output reg       ack,
  output reg [7:0] got
);
  always @(posedge clk) begin
    if (rst) begin
      ack <= 1'b0;
    end
    else if (req && !ack) begin            // phase 2: take the data, acknowledge
      ack <= 1'b1;
      got <= data;
    end
    else if (!req && ack) begin            // phase 4: drop the acknowledge
      ack <= 1'b0;
    end
  end
endmodule

The four-phase handshake works even when the two sides run on unrelated clocks, because each step waits for a level, not an edge. That makes it the standard way to pass a word across a clock domain boundary, as the bridges and clock domain crossing article shows. Its cost is speed: four signal changes per word.

Two-Phase Request/Acknowledge

The two-phase handshake, also called toggle signaling, halves the work. Every change of req, up or down, announces a new word, and every change of ack acknowledges it. The sender may send when req equals ack:

always @(posedge clk) begin
  if (rst) begin
    req <= 1'b0;
  end
  else if (go && req == ack) begin       // idle when req equals ack
    req  <= ~req;
    data <= din;
  end
end

The receiver copies req into ack whenever they differ, taking the data at the same time.

Valid/Ready

Inside a synchronous design, there is a faster option. The sender drives valid when it has data; the receiver drives ready when it can accept data. A word moves in every clock cycle in which both are high. There are no return-to-zero phases at all. Two rules keep it safe:

• Once the sender raises valid, it keeps valid high and the data unchanged until the word is taken.
• The sender must not wait for ready before raising valid; the receiver may wait for valid before raising ready. This prevents both sides from waiting for each other forever.

always @(posedge clk) begin
  if (rst) begin
    valid <= 1'b0;
    data  <= 8'h01;
  end
  else begin
    if (valid && ready)                  // the word was taken: offer the next one
      data <= data + 8'h01;
    if (!valid || ready)                 // never withdraw a word that is waiting
      valid <= go;
  end
end

AXI uses valid/ready on all five of its channels, and AXI-Stream is nothing but valid/ready plus data.

All Three Side by Side

The testbench runs all three handshakes on the same clock for the same ten cycles. The valid/ready receiver stalls for two of them.

Valid/ready reaches one word per cycle because the next word can follow immediately; the request/acknowledge handshakes spend cycles returning to an idle state or waiting for the other side to see each change.

Running It in ChipVerify Lab

The example contains the three sender and receiver pairs and the testbench that drives them. Run it and compare the three handshakes in the waveform.

Common Mistakes

repeat (5) begin                 // the receiver stalls in every second cycle
  @(negedge clk);
  stall = 1;
  @(negedge clk);
  stall = 0;
end