A burst tells the slave that several related transfers are coming, so a memory controller can open a row once, or a cache can fetch a whole line. Three AHB signals describe a burst: HTRANS marks each cycle as the start of a burst, a continuation, a pause or nothing; HBURST gives the burst type and length; and HSIZE gives the size of each beat. This article explains all three with waveforms of every common burst type.

10 min read | Intermediate

What You'll Learn

• Use the four HTRANS types: IDLE, BUSY, NONSEQ and SEQ
• Calculate the addresses of incrementing and wrapping bursts
• Choose HSIZE and put narrow data on the right byte lanes
• Apply the burst rules: 1 KB boundary, alignment and how a burst may end

HTRANS: the Transfer Type

HTRANS is driven in the address phase of every cycle and says what kind of transfer the address belongs to:

A single transfer is just a burst of length one, so it is always NONSEQ. Here is an incrementing write burst: the first beat is NONSEQ, the following beats are SEQ, and each address is 4 higher because the beats are words.

When the master cannot supply the next beat in time, it inserts BUSY. During BUSY the address already shows the next beat (0x14 here), and the data phase that follows a BUSY carries no data:

Two rules limit BUSY. A fixed-length burst must end with a SEQ beat, never with BUSY; only an undefined-length INCR burst may stop after a BUSY. And a master may not issue BUSY right after a SINGLE transfer, because there is no burst to continue.

HBURST: the Burst Type

The length counts beats, not bytes. The amount of data in a burst is the number of beats times the size of each beat. AHB has only two kinds of burst: incrementing, where each address is the previous one plus the beat size, and wrapping, which does the same but wraps inside an aligned block. There is no fixed-address burst in AHB; that is an AXI feature.

Incrementing Bursts

An INCR4 of words goes 0x10, 0x14, 0x18, 0x1C. This one has a BUSY before the second beat and is followed by IDLE:

A new burst can start straight after the last beat of the previous one, with NONSEQ instead of IDLE. Here a second INCR4 to 0x30 follows immediately:

An INCR burst has no fixed length: the master simply keeps issuing SEQ beats and ends the burst with IDLE or a new NONSEQ.

Wrapping Bursts

A wrapping burst stays inside an aligned block whose size is the number of beats times the beat size. A WRAP4 of words uses a 16-byte block, so a burst starting at 0x18 goes 0x18, 0x1C, then wraps to 0x10 and 0x14.

Wrapping bursts exist for caches. A processor that misses on address 0x18 wants that word first, but the cache line it fills covers 0x10 to 0x1F. A wrapping burst returns the critical word first and still fills the whole line.

The waveforms below come from a simulation of the memory slave used in this chapter. It inserts one wait state on the first beat of each burst and none on the others. Notice that the second address is held for two cycles and the first write data stays on HWDATA through the wait.

WRAP8 of words uses a 32-byte block. Starting at 0x58, the burst runs to 0x5C and then wraps to 0x40:

WRAP16 of words uses a 64-byte block. Starting at 0x70, it runs to 0x7C and wraps to 0x40:

HSIZE: the Beat Size

HSIZE must not be larger than the data bus, so a 32-bit bus only uses byte, halfword and word. It has the timing of the address and must stay constant through a burst. Together with HBURST it sets the wrap boundary: smaller beats mean a smaller block.

A narrow transfer uses only some byte lanes of the bus. On a little-endian 32-bit bus, the lane is given by the low address bits: a byte at an address ending in 1 travels on HWDATA[15:8], and a halfword at an address ending in 2 travels on HWDATA[31:16]. The master only has to drive the active lanes, and the slave picks its data from them.

WRAP16 of halfwords uses a 32-byte block. Starting at 0x76, it runs to 0x7E and wraps to 0x60:

The Burst Rules

• 1 KB boundary: a master must not start an incrementing burst that crosses a 1 KB address boundary. Slave address regions are at least 1 KB and start on 1 KB boundaries, so a burst never leaves the slave it started in.
• Alignment: every beat is aligned to its size. Word beats have HADDR[1:0] = 00, halfword beats have HADDR[0] = 0.
• Constant control: HWRITE, HSIZE, HBURST and HPROT stay the same for every beat.
• Early end: a master may stop a burst after an ERROR response. A slave must also cope with a burst that is cut short, because a multi-layer interconnect can end one to let another master in.

The Simulation

The testbench writes three WRAP4 bursts of words, halfwords and bytes, then reads the first block back with an INCR4:

burst(1, WRAP4, 32'h018, WORD, 4, 32'h10);    // 0x18, 0x1C, 0x10, 0x14
burst(1, WRAP4, 32'h042, HALF, 4, 32'h1110);  // 0x42, 0x44, 0x46, 0x40
burst(1, WRAP4, 32'h049, BYTE, 4, 32'h20);    // 0x49, 0x4A, 0x4B, 0x48
burst(0, INCR4, 32'h010, WORD, 4, 0);         // 0x10, 0x14, 0x18, 0x1C

45  write 0x0018 = 0x00000010  OKAY
55  write 0x001c = 0x00000011  OKAY
65  write 0x0010 = 0x00000012  OKAY
75  write 0x0014 = 0x00000013  OKAY
105  write 0x0042 = 0x11100000  OKAY
115  write 0x0044 = 0x00001111  OKAY
125  write 0x0046 = 0x11120000  OKAY
135  write 0x0040 = 0x00001113  OKAY
165  write 0x0049 = 0x00002000  OKAY
175  write 0x004a = 0x00210000  OKAY
185  write 0x004b = 0x22000000  OKAY
195  write 0x0048 = 0x00000023  OKAY
225  read  0x0010 = 0x00000012  OKAY
235  read  0x0014 = 0x00000013  OKAY
245  read  0x0018 = 0x00000010  OKAY
255  read  0x001c = 0x00000011  OKAY

The INCR4 read returns the words in address order, so you can see where the wrapping write put them: 0x12 at 0x10, because it was the third beat. Each burst pays for its wait state only once, on the first beat.

Running It in ChipVerify Lab

The example runs these four bursts. Compare the HADDR sequence of each burst with the wrap boundary for its HSIZE.

Common Mistakes

burst(1, WRAP8, 32'h03A, HALF, 8, 32'h500);

45  write 0x003a = 0x05000000  OKAY
55  write 0x003c = 0x00000501  OKAY
65  write 0x003e = 0x05020000  OKAY
75  write 0x0030 = 0x00000503  OKAY
85  write 0x0032 = 0x05040000  OKAY
95  write 0x0034 = 0x00000505  OKAY
105  write 0x0036 = 0x05060000  OKAY
115  write 0x0038 = 0x00000507  OKAY