Bus Transfers: Reads, Writes, Wait States, Errors and Bursts

Every bus moves data in transfers, and every transfer is a read or a write. Around that simple core, all bus protocols deal with the same four situations: a slave that answers at once, a slave that needs more time, a transfer that fails, and a series of transfers to consecutive addresses. This article explains each one on the teaching bus, with the waveforms from the simulation, so that the APB, AHB and AXI chapters can focus on what is specific to each protocol.

9 min read | Beginner

What You'll Learn

• Describe the timing of a basic read and write
• Explain wait states and how a slave inserts them
• Explain error responses and where they come from
• Explain bursts and why buses support them

Reads and Writes

In a write, the master provides the address and the data, and the slave stores the data. In a read, the master provides the address, and the slave returns the data. On the teaching bus, the master drives sel, we, addr and, for a write, wdata; the transfer ends at the rising clock edge where the slave's ready is 1. In that cycle, a write is stored and read data is valid on rdata.

With a slave that is always ready, a transfer takes one cycle. The register slave of the teaching bus is like that: the write of 0xA5 to register 1 and the read back each take a single cycle in the waveform of the first article.

Wait States

Many slaves cannot answer in one cycle: a memory may need time to read its array, a peripheral may be busy, a bridge may have to forward the request to a slower bus. The slave then holds ready low. Each cycle with ready low is a wait state, and the master keeps all its signals steady until ready goes high.

The memory slave of the teaching bus inserts one wait state per transfer. A memory write therefore takes two cycles: one with ready low, one with ready high. Almost every bus uses this idea under a different name: PREADY in APB, HREADY in AHB, the READY signals of AXI.

Error Responses

A transfer can fail: the address belongs to no slave, the slave does not support the access (a write to a read-only register, for example), or the slave detected a problem such as a parity error in its memory. The slave, or the default slave of the decoder, then completes the transfer with an error indication. On the teaching bus that is err = 1 in the completing cycle; APB calls it PSLVERR, AHB HRESP = ERROR, AXI the SLVERR and DECERR responses.

An error still completes the transfer: the master must not wait. What happens next is up to the master. A processor usually raises a bus fault exception, and the software decides how to recover.

Bursts

Masters often access consecutive addresses: a processor fills a cache line of 32 or 64 bytes, a DMA engine copies a block of memory. A burst is a series of transfers to consecutive addresses. The teaching bus has no special support, so the master simply keeps sel high and moves the address on after each completed beat:

35  beat 0: write addr=14 data=10
55  beat 1: write addr=15 data=20
75  beat 2: write addr=16 data=30
95  beat 3: write addr=17 data=40

Four beats take eight cycles, because the memory inserts a wait state for every beat. A bus with real burst support tells the slave at the start how long the burst is and how the addresses advance. The slave can then prepare the next beat while finishing the current one, for example by reading the next memory word in advance, and the wait states disappear after the first beat. AHB announces bursts with HBURST and HTRANS; AXI sends one address with a length for a whole burst.

Two burst address patterns appear in every bus:

• Incrementing: each beat goes to the next address, as here.
• Wrapping: the addresses wrap at a boundary, so a cache can fetch the word it needs first and then the rest of its line. For a 4-beat wrapping burst of bytes starting at 0x16: 0x16, 0x17, 0x14, 0x15.

Running It in ChipVerify Lab

The example runs a four-beat write burst into the memory, reads two of the bytes back, and reads an unmapped address. Run it and follow the beats and the error in the waveform.

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