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What is testbench top module ?

All verification components, interfaces and DUT are instantiated in a top level module called testbench. It is a static container to hold everything required to be simulated and becomes the root node in the hierarchy.

top-module

Simulators typically need to know the top level module so that it can analyze components within the top module and elaborate the design hierarchy.

Click here to know more about top level modules !

Testbench Top Example

The example below details the elements inside the top module tb_top.

 
module tb_top;
   import uvm_pkg::*;
 
   // Complex testbenches will have multiple clocks and hence multiple clock
   // generator modules that will be instantiated elsewhere
   // For simple designs, it can be put into testbench top
   bit clk;
   always #10 clk <= ~clk;
 
 
   // Instantiate the Interface and pass it to Design
   dut_if         dut_if1  (clk);
   dut_wrapper    dut_wr0  (._if (dut_if1));
 
 
   // At start of simulation, set the interface handle as a config object in UVM 
   // database. This IF handle can be retrieved in the test using the get() method
   // run_test () accepts the test name as argument. In this case, base_test will
   // be run for simulation
   initial begin
      uvm_config_db #(virtual dut_if)::set (null, "uvm_test_top", "dut_if", dut_if1);
      run_test ("base_test");
   end
 
   // Multiple EDA tools have different system task calls to specify and dump waveform
   // in a given format or path. Some do not need anything to be placed in the testbench
   // top module. Lets just dump a very generic waveform dump file in *.vcd format
   initial begin
       $dumpvars;
       $dumpfile("dump.vcd");
   end
 
endmodule
 

Note the following :

  • tb_top is a module and is a static container to hold everything else
  • It is required to import uvm_pkg in order to use UVM constructs in this module
  • Clock is generated in the testbench and passed to the interface handle dut_if1
  • The interface is set as an object in uvm_config_db via set and will be retrieved in the test class using get methods
  • The test is invoked by run_test method which accepts name of the test class base_test as an argument
  • Call waveform dump tasks if required

Learn how run_test() starts the actual UVM test from this blog post.

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