Transaction Level Modeling, is a modeling style for building highly abstract models of components and systems. In this scheme, data is represented as transactions (class objects that contain random, protocol specific information) which flow in and out of different components via special ports called TLM interfaces. This brings about a higher level of abstraction which is very much required in today's verification environments because of the large amount of signals associated with different protocols. It would be a lot simpler to understand, debug and verify if we can represent data and changes in signals as transactions (like write operation/read operation).

UVM provides a set of transaction-level communication interfaces that can be used to connect between components such that data packets can be transferred between them. The good part about this setup is that it isolates a component from the changes in other components, and promotes reusability and flexibility because now you can just swap a component with another which also have a TLM interface.

class simple_packet extends uvm_object;
	`uvm_object_utils (simple_packet)
	rand bit [7:0] addr;
	rand bit [7:0] data;
		 bit 		rwb;
	constraint c_addr { addr > 8'h2a; };
	constraint c_data { data inside {[8'h14:8'he9]};

simple_packet class object will be a transaction that can be sent from componentA to componentB via TLM interface ports port and export.