UVM accelerates the development process and facilitates re-use. Inorder to create a testbench from UVCs, you'll need to

  • Review the configuration parameters of each UVC
  • Instantiate and configure UVCs
  • Create re-usable sequences for interface components
  • Add a virtual sequencer
  • Add checking and functional coverage extensions
  • Create tests to cover all functionalities
It's always better to instantiate verification components in a separate container uvm_env, because if you instantiate components inside the tests uvm_test, it does not facilitate modularity, flexibility and will become difficult to maintain later on. Here are a few more drawbacks:
  • Test writer must know how to configure the environment, and will need to know the specifics of each UVC.
  • Multiple files will have to be edited, if the topology needs to be changed.
  • Tests cannot be ported or re-used since topology and testbench requirements will widely vary between projects.
Multiple tests can instantiate the same testbench class.