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This session is a real example of how design and verification happens in the real industry. We'll go through the design specification, write a test plan that details how the design will be tested, develop a UVM testbench structure and verify the design.

Design

This is a simple pattern detector written in Verilog to identify a pattern in a stream of input values. On every clock, there is a new input to the design and when it matches the pattern '1011', the output out will be set to 1. For this purpose, the design is implemented as a state machine which moves through different stages as it progresses through pattern identification sequence.

Test Plan

The verification testbench will be developed in UVM and has the following block diagram:

  • The sequence generates a random stream of input values that will be passed to the driver as a uvm_sequence_item
  • The driver receives the item and drives it to the DUT through a virtual interface
  • The monitor captures values on the DUT's input and output pin, creates a packet and sends to the scoreboard
  • The scoreboard is primarily responsible for checking the functional correctness of the design based on the input and output values it receives from the monitor.

The input stream of values has to be random for maximum efficiency. It should be able to catch the following scenarios:

  • 011011011010
  • 101011100
  • 111011011

Testbench

Sequence Item

 
// This is the base transaction object that will be used
// in the environment to initiate new transactions and 
// capture transactions at DUT interface
class Item extends uvm_sequence_item;
  `uvm_object_utils(Item)
  rand bit  in;
  bit     out;
 
  virtual function string convert2str();
    return $sformatf("in=%0d, out=%0d", in, out);
  endfunction
 
  function new(string name = "Item");
    super.new(name);
  endfunction
 
  constraint c1 { in dist {0:/20, 1:/80}; }
endclass
 

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