Half-Cycle Paths

Most paths launch and capture on the same clock edge type, so the data has a full clock period. When a path launches on one edge and captures on the opposite edge, it only has half of a period. Such a path is called a half-cycle path. It appears when a design uses both rising-edge and falling-edge flip-flops, with clock gating enables, or with latches. This article shows how STA chooses the edges of a half-cycle path, what the time budget is, and how the duty cycle of the clock affects it.

8 min read | Intermediate

What You'll Learn

• Recognize a half-cycle path and name its launch and capture edges
• Calculate the setup and hold slack of a path from a rising-edge to a falling-edge flip-flop
• Explain why the duty cycle of the clock matters for half-cycle paths
• Read the edge types in a half-cycle report

The Design

Two flip-flops, one clocked on the rising edge and the second on the falling edge:

module sta_half (input clk, d, output q);
  reg r1, r2;
  always @(posedge clk) r1 <= d;
  always @(negedge clk) r2 <= r1;
  assign q = r2;
endmodule

The synthesis tool builds the falling-edge flip-flop from a rising-edge flip-flop with an inverter in front of its clock pin. STA looks through the inverter and handles the clock edge correctly: the falling edge of clk becomes the rising edge at the pin of r2.

Setup of a Half-Cycle Path

The first flip-flop launches data on the rising edge at time 0. The second flip-flop captures on the falling edge of the clock. The first falling edge after the launch is at 1.0 ns, half a period later. The setup check uses this edge:

The numbers: the data arrives at 0.2688 ns (the clock-to-Q delay), and the required time is 1.0 - 0.1112 = 0.8888 ns, with a setup time of 0.1112 ns. The setup slack is 0.8888 - 0.2688 = 0.6200 ns. If the same path were between two rising-edge flip-flops, the required time would be 2.0 - 0.1112 = 1.8888 ns and the slack 1.62 ns. Half of the period is gone, and the slack is 1.0 ns smaller.

The Duty Cycle Decides the Time

The falling edge is at half of the period only for a clock with 50 percent duty cycle. For a clock created with -waveform {0 0.5}, the falling edge is at 0.5 ns, and the data has only 0.5 ns:

create_clock -name clk -period 2.0 -waveform {0 0.5} [get_ports clk]

The required time is 0.5 - 0.1112 = 0.3888 ns, and the setup slack of the half-cycle path is 0.3888 - 0.2688 = 0.1200 ns. The slack falls from 0.6200 ns to 0.1200 ns, a difference of 0.5 ns, the same as the time that the falling edge moved. This is why the duty cycle in the clock definition matters for designs with both edges, while it did not matter for rising-edge paths in the article about defining clocks.

Hold of a Half-Cycle Path

For hold, STA looks for the capture edge that comes before or at the launch edge that follows. The launch edge for the hold check is at 2.0 ns, the next rising edge. The capture edge that it must not disturb is the falling edge at 1.0 ns, the one before it. The required time is 1.0 - 0.0346 = 0.9654 ns, and the data launched at 2.0 ns arrives at 2.2749 ns. The hold slack is 2.2749 - 0.9654 = 1.3096 ns, a large margin. In this direction, the data has a lot of time to spare for hold. The hold check of a half-cycle path is rarely a problem, and the setup check is the one to watch.

The Other Direction

A path from the falling-edge flip-flop to a rising-edge flip-flop or to an output is also a half-cycle path. In the demo, the output q is launched at the falling edge at 1.0 ns. It arrives at 1.0 + 0.2615 = 1.2615 ns. The output delay of 0.4 ns is measured against the next rising edge at 2.0 ns, so the required time is 1.6 ns, and the slack is 0.3385 ns. The same flip-flop, driven by a rising edge, would have a slack of 1.3385 ns, 1.0 ns more.

Where Half-Cycle Paths Come From

• Falling-edge flip-flops, used for interfaces or for clock-domain tricks.
• Clock gating enables from a falling-edge flip-flop, as shown in the article about clock gating checks.
• Latches, whose closing edge is half a period after the opening edge.
• Paths between the two phases of a design that uses both phases of the clock.

Reading the Report

The report names the edge type at every end, and the clock rows show which edge launches and which captures. For the half-cycle path of this design, the capture row of the setup report is at 1.0 ns, and it is marked as the fall edge of clk. If you see a capture time that is half of the period in a report that you did not expect, look for a falling-edge flip-flop or a latch.

Common Mistakes

create_clock -name clk -period 2.0 -waveform {0 0.5} [get_ports clk]