Your First OpenSTA Run

The earlier articles explained what the numbers in a timing report mean. This article is where you produce one yourself. You will take a very small design, give it a clock and the delays at its ports, run OpenSTA on it, and read the result line by line. The same five steps are used for the large designs later in this chapter, so it is worth doing them once on something small.

9 min read | Intermediate

What You'll Learn

• List the five steps of an OpenSTA run and say what each command does
• Write a minimal SDC file with a clock, input delays and output delays
• Read a setup report and a hold report and find the launch edge, the capture edge and the slack
• Predict the new slack when the clock period changes

The Design

The design has two flip-flops, an XOR gate and an OR gate. It is small enough that every cell in the report can be matched to a line of Verilog:

module sta_demo (input clk, input a, b, c, d, output y, z);
  reg r1, r2;
  always @(posedge clk) r1 <= a & b;     // input -> register
  always @(posedge clk) r2 <= r1 ^ c;    // register -> register (c: input -> register)
  assign y = r1 & r2;                    // register -> output
  assign z = a | d;                      // input -> output
endmodule

It has all four kinds of timing path from the article about timing paths: input to register, register to register, register to output and input to output.

The Five Steps

OpenSTA does not read Verilog source code. It reads a gate-level netlist, which is the design after synthesis, where every line is a cell from the standard cell library. The ChipVerify Lab runs the synthesis tool for you and then starts OpenSTA, so you can paste the RTL above. The OpenSTA part of the run is these commands:

read_liberty sky130_fd_sc_hd__tt_025C_1v80.lib   ;# 1. the cell delays and setup/hold times
read_verilog netlist.v                            ;# 2. the gate-level netlist
link_design sta_demo                              ;# 3. connect the netlist to the library cells
read_sdc demo.sdc                                 ;# 4. the constraints
report_checks -path_delay max                     ;# 5. ask for results

• read_liberty loads the library. Without it, OpenSTA does not know the delay of any cell. This one is the typical corner of the sky130 library (25 C, 1.80 V).
• read_verilog loads the netlist, and link_design says which module is the top, and connects every cell in it to its library description.
• read_sdc loads the constraints. They are explained next.
• report_checks (and the other report commands) calculate the timing and print it.

A run prints the warning that default_fanout_load is 0.0 for the library. It comes from the library file and can be ignored in this tutorial.

The Constraints

STA knows how fast the cells are, but it does not know how fast you want the chip to run, or when data arrives at the ports. The SDC file tells it:

create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay 0.4 -clock clk [get_ports {a b c d}]
set_output_delay 0.4 -clock clk [get_ports {y z}]

• create_clock defines a clock called clk on the port clk, with a period of 2.0 ns. The rising edge is at 0 and the falling edge at 1.0 ns.
• set_input_delay says that the data at the inputs changes 0.4 ns after the clock edge, as it comes from a register outside the chip.
• set_output_delay says that the circuit outside needs the outputs 0.4 ns before the next clock edge, which is its setup time.

The article about SDC covers these commands in detail. For now, remember that every path needs a start and an end that STA knows about. Without the input delays and output delays, the paths from and to the ports would not be checked at all.

Check That the Constraints Are Complete

Before you read the results, ask OpenSTA whether anything is missing:

check_setup -verbose

It prints nothing for this design, which means that every input has an input delay, every output has an output delay and every register has a clock. If you remove the set_output_delay line, it prints a warning that the outputs y and z are missing an output delay, and lists them. Always read this output first. A report with a good slack is worth nothing if half of the design was not checked.

Read the Setup Report

The command report_checks -path_delay max prints the worst setup path. For the demo it is the path from the input a to the output z:

Startpoint: a (input port clocked by clk)
Endpoint: z (output port clocked by clk)
Path Group: clk
Path Type: max

    Delay      Time   Description
-------------------------------------------------------------
   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.4000    0.4000 v input external delay
   0.0000    0.4000 v a (in)
   0.1674    0.5674 v _2_/X (sky130_fd_sc_hd__or2_0)
   0.0000    0.5674 v z (out)
             0.5674   data arrival time

   2.0000    2.0000   clock clk (rise edge)
   0.0000    2.0000   clock network delay (ideal)
   0.0000    2.0000   clock reconvergence pessimism
  -0.4000    1.6000   output external delay
             1.6000   data required time
-------------------------------------------------------------
             1.6000   data required time
            -0.5674   data arrival time
-------------------------------------------------------------
             1.0326   slack (MET)

The report has two halves. The first half is the data path: it starts at the launch edge (time 0), adds the input delay of 0.4 ns, and then the delay of the OR cell, 0.1674 ns. The data arrives at the output at 0.5674 ns. The second half is the capture side: the next clock edge is at 2.0 ns, and the 0.4 ns output delay is taken away, so the data is required by 1.6 ns. The slack is the required time minus the arrival time: 1.6000 - 0.5674 = 1.0326 ns. A positive slack means the path is met.

The arrow symbols ^ and v show whether the signal rises or falls at that point. STA checks both, and shows the worse one.

See It on a Waveform

The path that goes through two flip-flops shows the idea of launch and capture better. This is the register to register path from _7_ (the flop r1) to _6_ (the flop r2), with the same numbers as the reports of this article:

The launch flop starts the data at its clock edge at 0. The data leaves the flop 0.2874 ns later, goes through the XOR gate, and arrives at the D pin of the capture flop at 0.4323 ns. The capture flop takes the value at its own clock edge, at 2.0 ns, and needs it to be stable for its setup time of 0.1174 ns before that. The slack is the distance between the arrival and that point: 1.8826 - 0.4323 = 1.4502 ns.

Read the Hold Report

The hold check is the same path, with the earliest arrival and the same clock edge. It is printed with report_checks -path_delay min:

Startpoint: _7_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _6_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

    Delay      Time   Description
-------------------------------------------------------------
   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.0000    0.0000 ^ _7_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.3058    0.3058 ^ _7_/Q (sky130_fd_sc_hd__dfxtp_1)
   0.0599    0.3657 v _4_/X (sky130_fd_sc_hd__xor2_1)
   0.0000    0.3657 v _6_/D (sky130_fd_sc_hd__dfxtp_1)
             0.3657   data arrival time

   0.0000    0.0000   clock clk (rise edge)
   0.0000    0.0000   clock network delay (ideal)
   0.0000    0.0000   clock reconvergence pessimism
             0.0000 ^ _6_/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.0583   -0.0583   library hold time
            -0.0583   data required time
-------------------------------------------------------------
            -0.0583   data required time
            -0.3657   data arrival time
-------------------------------------------------------------
             0.4241   slack (MET)

For hold, the capture edge is the same edge as the launch edge (time 0), not the next one. The data arrives at 0.3657 ns, and the capture flop needs it to stay unchanged until its hold time has passed, which is at -0.0583 ns (the hold time of this flop is negative). The slack is the arrival minus the required time: 0.3657 - (-0.0583) = 0.4241 ns.

The Summary Commands

A report of the single worst path is not always what you need. These commands give the whole design in a few lines:

report_worst_slack -max     ;# worst setup slack of the design
report_worst_slack -min     ;# worst hold slack of the design
report_tns                  ;# total negative slack: sum of all violations (0 if none)
report_wns                  ;# worst negative slack (0 if none)

For the demo they print 1.03 and 0.42 for the two worst slacks, and 0.00 for the total and the worst negative slack, because nothing is violated. The word negative in the last two names is the key: they only count paths that fail. A run with a total negative slack of 0 is a run where every path is met.

Common Mistakes