The Metal Stack: Layers, Vias and Pitches

Above the transistors of a chip sits a stack of metal layers separated by insulator and connected by vias. The router draws every signal wire on these layers, and the power grid uses them too. Each layer has a preferred direction, a pitch, a minimum width, a thickness and a resistance, and these numbers decide how many wires fit, how fast signals travel and where power should run. This article describes the sky130 metal stack with the real values from its technology LEF and shows how a routed design uses the layers.

8 min read | Beginner

What You'll Learn

• Name the routing layers and cut layers of the sky130 process
• Explain preferred routing direction, pitch and minimum width
• Calculate the resistance of a wire from its sheet resistance
• Explain why lower layers carry local wires and upper layers carry power and long wires

The sky130 Stack

sky130 has six interconnect layers. From the bottom:

• li1 (local interconnect): a thin, resistive layer used inside standard cells and for their pins.
• met1 and met2: thin layers with a tight pitch, for short local wires. met1 also carries the power rails of the rows.
• met3 and met4: thicker layers for longer connections and power straps.
• met5: the thickest and widest layer, mostly used for power and for long, fast wires.

Between the layers are cut layers, which hold the vias: mcon connects li1 to met1, via connects met1 to met2, and via2, via3 and via4 connect the higher pairs. A via is a small square hole in the insulator filled with metal.

Direction, Pitch and Width

Each routing layer has a preferred direction, and the directions alternate: met1 horizontal, met2 vertical, met3 horizontal, met4 vertical, met5 horizontal. A wire that has to turn a corner simply changes layer through a via. Alternating directions let wires on neighbouring layers cross without touching, and keep the wiring regular.

The pitch is the distance from the centre of one routing track to the next: 0.34 um on met1, 0.46 um on met2, 0.68 um on met3, 0.92 um on met4 and 3.40 um on met5. It is the minimum width plus the minimum spacing between two wires. Pitch decides how many wires fit: across 10 um of height, met1 offers 29 horizontal tracks, while met5 offers only 2 or 3.

In the technology LEF, a layer is described like this:

LAYER met1
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
  PITCH 0.34 ;
  WIDTH 0.14 ;
  THICKNESS 0.35 ;
  RESISTANCE RPERSQ 0.125 ;
  ...
END met1

Resistance of a Wire

The LEF gives each layer's sheet resistance in ohms per square. A wire of length L and width W has L / W squares, so its resistance is R = R_sq x L / W. For 100 um of minimum-width wire:

li1 is about 80 times worse than met1 for the same length, which is why it is only used inside cells and for very short hops. met5 is 50 times better than met1, because it is thicker and wider. That is the reason power grids and long, timing-critical wires go to the upper layers, and the power straps in this tutorial sit on met4 and met5.

How a Routed Design Uses the Layers

This is a 16x16 multiplier, about 1,600 cells, after routing in the lab's flow. The left half shows only its met1 wires, the right half only its met2 wires. met1 wires run horizontally and met2 wires vertically, as the preferred directions say. Of the 28.3 mm of signal wire in the design, 13.2 mm is on met1, 14.3 mm on met2, 0.67 mm on met3 and 0.11 mm on met4. A design this small rarely needs the upper layers for signals; a large chip uses all of them.

Running It in ChipVerify Lab

The example is the 16x16 multiplier, which fits within the free cell limit. Synthesize it, run Place and Route, and use the layer controls of the layout viewer to show one metal layer at a time.

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