Macro Placement: Halos and Channels

Many designs contain macros: large, pre-built blocks such as SRAMs, register files, PLLs or analog IP that are placed as a whole. A macro is often bigger than all the standard cells around it, so where it goes and which way it faces shapes the entire floorplan. This article explains how macros are placed, why they need halos and channels, and shows with a real sky130 SRAM how the orientation of a macro changed the wire length of a design by 40 %.

9 min read | Intermediate

What You'll Learn

• Explain what a hard macro is and how it appears in LEF and DEF
• Place a macro with a location and orientation in OpenROAD
• Explain halos, channels and cutting rows around a macro
• Choose a macro orientation from its pin locations

Hard Macros

A hard macro is a finished layout with a fixed size and fixed pins, delivered like a standard cell but much larger. In its LEF it has CLASS BLOCK, a size, pins and obstructions; it also has its own Liberty file for timing and its own GDS. The SRAM used in this article, sky130_sram_1rw1r_44x64_8, is 64 words of 44 bits with one read-write port and one read port, generated with OpenRAM. Its LEF:

MACRO sky130_sram_1rw1r_44x64_8
   CLASS BLOCK ;
   SIZE 445.24 BY 237.415 ;
   PIN din0[0]
      DIRECTION INPUT ;
      PORT
         LAYER met2 ;
         RECT  102.095 2.69 102.425 2.95 ;
   ...

It is 445 x 237 um, about 105,700 um², ten times the area of the whole 16x16 multiplier. Its obstructions cover met1 to met3, so wires may still cross over it on met4 and met5. Its power pins, vdd and gnd, are on met3.

The Example

A small wrapper registers the address and data, writes into the SRAM and registers the read data with a little logic after it. Synthesis treats the SRAM as a black box (an empty module marked (* blackbox *)), and place and route reads its LEF and Liberty. The die is 620 x 400 um. Two inputs of the SRAM are tied to constants (the second port's chip select, the write mask), so synthesis must insert tie cells (conb_1); without them the router stops on an undriven constant net.

Placing the Macro

Macros are placed after the floorplan and before the power grid and the standard cells:

place_macro -macro_name u_sram -location {30.36 32.64} -orientation R0
cut_rows -halo_width_x 5 -halo_width_y 5

place_macro fixes the macro at a location and orientation; its status in DEF becomes FIXED, so later steps cannot move it. cut_rows removes the row segments under the macro plus a 5 um halo around it, so no standard cell lands on the macro or right against its edges. The power grid then needs a macro grid that connects the SRAM's met3 power pins to the met4 straps above it:

add_global_connection -net VDD -inst_pattern u_sram -pin_pattern vdd -power
add_global_connection -net VSS -inst_pattern u_sram -pin_pattern gnd -ground
define_pdn_grid -name sram -macro -instances u_sram -halo {5 5 5 5} -voltage_domains CORE -grid_over_boundary
add_pdn_connect -grid sram -layers {met3 met4}

For designs with many macros, OpenROAD also has an automatic macro placer, rtl_macro_placer. Even then, designers usually fix the big macros by hand, because their position defines the floorplan.

Orientation Matters

The SRAM's signal pins sit near one of its long edges: din0[0], for example, is 2.69 um above the bottom edge. In the first run, with orientation R0, that edge faces the bottom of the die. The logic, the I/O pins and the registers sit above the macro, so every connection to the SRAM runs across it, down to the pins at the bottom: you can see the bundle of met4 wires (purple) crossing the macro. In the second run the macro is flipped (orientation MX, written as FS in DEF), so its pins face up towards the logic:

Flipping the macro cut the wire length by 40 % and freed 8 mm of met4 that the first run used to cross it. In a design where the SRAM access is the critical path, the shorter wires would also matter for timing.

Channels

When macros are placed next to each other or near the die edge, the gap between them is a channel. Wires to the macro pins and wires passing by must fit in it. A channel that is too narrow becomes the most congested part of the chip; one that is too wide wastes area. The rule of thumb is to estimate the number of wires that must pass, divide by the number of free tracks per micron on the routing layers, and add the halos. Placing macros at the edges and corners of the core, pins facing inwards, keeps one large contiguous area for standard cells and avoids most channel problems.

Running It in ChipVerify Lab

The lab's PnR panel does not place macros yet; the runs in this article used the same OpenROAD flow with the SRAM files that come with OpenROAD-flow-scripts. The example contains the wrapper and the black-box SRAM module: synthesize it to see how the SRAM is kept as a black box and which cells surround it.

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