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Verification
Basic Concepts
  Introduction
  Verification Techniques
  Verification Stages
  Directed Verification
  Constraint Random Verification
  Assertion Based Verification

Verification Plan
  Verification Plan

Testbench
  Testbench Evolution
  Linear Testbench
  File Based Testbench
  State Machine Testbench
  Linear Random Testbench
  Self Checking Testbench

Code Coverage
  Code Coverage
  Block Coverage
  Statement Coverage
  Expression Coverage
  Toggle Coverage
  Assertion Coverage
  Unreachable Code Coverage

Toggle Coverage

Toggle coverage is a type of code coverage that measures the percentage of signal transitions observed during the simulation. Here's an example of toggle coverage RTL code:

Read more: Toggle Coverage

Expression Coverage

Expression coverage is a type of code coverage that measures the percentage of Boolean expressions executed during the simulation. Here's an example of expression coverage RTL code:

Read more: Expression Coverage

Statement Coverage

Statement coverage is a type of code coverage that measures the percentage of code statements executed during the simulation. Here's an example of statement coverage RTL code:

Read more: Statement Coverage

Block Coverage

Block coverage is a type of code coverage that measures the percentage of basic blocks executed during the simulation. A basic block is a continuous sequence of code statements with a single point of entry and a single point of exit.

Read more: Block Coverage

Code Coverage

Code coverage is a crucial component of verification, and it is used to ensure that the design-under-test (DUT) is properly tested. Code coverage helps to identify untested or under-tested parts of the design, which may contain bugs or errors that could impact the functionality of the design.

Read more: Code Coverage

  1. Constraint Random Verification
  2. Directed Verification
  3. Verification Techniques
  4. Self Checking Testbench
  5. Linear Random Testbench

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Related Topics
  Digital Fundamentals
  Verilog Tutorial

  Verification
  SystemVerilog Tutorial
  UVM Tutorial
  • Verilog Testbench
  • Verilog Coding Style Effect
  • Verilog Conditional Statements
  • Verilog Interview Set 10
  • Synchronous FIFO
  • SystemVerilog Interview Set 10
  • SystemVerilog Interview Set 9
  • SystemVerilog Interview Set 8
  • SystemVerilog Interview Set 7
  • SystemVerilog Interview Set 6
  • UVM Singleton Object
  • UVM Component [uvm_component]
  • UVM Object [uvm_object]
  • UVM Root [uvm_root]
  • UVM Interview Set 4
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