Practice and Preparation is quite essential for anyone looking for a job as a verification engineer. Here, you may find the most frequently asked Interview Questions on SystemVerilog, UVM, Verilog, SoC
p_sequencer is a handle to the sequencer on which the current sequence should be executed and is made available in a sequence by the macro `uvm_declare_p_sequencer.
What is a UVM RAL model ? Why is it required ?
RAL is short for Register Abstraction Layer. It is a set of base classes that can be used to create register models to mimic the register contents in a design. It is much easier to write and read from the design using a register model than sending a bus transaction for every read and write. Also the register model stores the current state of the design in a local copy called as a mirrored value. Read more in Register Layer.
What is an analysis port ?
An analysis port is a TLM mechanism to allow a component to broadcast a class object to multiple listeners so that they can implement different methods to perform different operations on the data it receives. Read more in TLM Analysis Port
What is the difference between new() and create() ?
No. UVM is built on SystemVerilog and hence you cannot run UVM with any tool that does not support SystemVerilog.
Why do we need to register a class with a factory ?
You don't necessarily need to. It is registered with a factory simply to make the testbench more re-usable and have the capability to override it with some other derivative component later on. Read more in Using factory overrides.
What are Active and Passive modes in an agent ?
An agent typically consists of a driver, sequencer and a monitor. At times, we don't want the agent to drive anything to the DUT but simply monitor the signals on the interface. This is a passive agent where sequencer and driver are not instantiated at all. An active agent is when it can run sequences on its sequencer, drive signals and monitor the interface. Read more in How to change an agent from active to passive ?
What is a TLM Fifo ?
When two components at different clocks need to be operating independently, you have to insert a TLM FIFO in between. One component can send data at a faster rate while the other component can receive at a slower rate. Read more in TLM Fifo
What are the advantages of `uvm_component_utils and `uvm_object_utils ?
These macros are used to register a class with the factory. `uvm_component_utils is used when the class is a component derived from uvm_component, and `uvm_object_utils is used if it's an object derived from uvm_object. There are no advantages from one over the other but are separate ways to register with the factory. Read more in Using factory overrides.
What is a virtual sequence and a virtual sequencer ?
A virtual sequence is a container to hold and execute multiple other smaller sequences. A virtual sequencer is a container to hold the handles to other sequencers in an environment so that each sequence in a virtual sequence can be executed on the appropriate sequencer. Read more in Virtual Sequence and Virtual Sequencer
What is the difference between `uvm_do and `uvm_send ?
What is the difference between uvm_transaction and uvm_sequence_item ?
The uvm_transaction class is the root base class for UVM transactions and has a timing and recording interface as well. Use of this class as a base for user-defined transactions is deprecated, and instead its sub-class uvm_sequence_item should be used. The intended use of transaction API is to call accept_tr, begin_tr and end_tr during the course of sequence item execution in order to record the events to a vendor-specific transaction database. uvm_sequence_item is primarily used to define data objects and related methods.
What are the benefits of using UVM ?
Some of the major and immediate benefits are :
Testbench prototyping becomes faster because of all the base classes for drivers, monitors, sequencers
There's a well defined reporting system which supports various levels of verbosities like LOW, DEBUG, etc
Supports register model creation and maintainence which simplifies the way DUT registers are accessed
Well structured plug and play style components like agents that can be plugged into any environment to support a particular protocol
Factory helps to override certain components without having to modify existing connections in the testbench
Configuration databases that allow components to share objects and data between each other
Make use of TLM features that enable different components that receive transactions to perform different operations on it.
Promotes re-usability, flexibility, uniformity and robustness to every testbench built on UVM
Can we have a user defined phase in UVM ?
Yes, you can define your own phase and insert it between any of the existing phases. For this, you have to first define a new phase class inherited from uvm_task_phase, implement the exec_task or exec_func method and insert the phase into existing schedule or domain object.
What is the difference between RAL backdoor and frontdoor accesses ?
A backdoor access in RAL is a way to dump values directly onto the DUT registers via a hard coded RTL signal path and does not consume simulation time. A frontdoor access in RAL is usually done by sending the data as a transaction through an associated peripheral bus interface and hence consumes simulation time.
What is a phase objection ?
In UVM, all components synchronize with each other through a set of phases. Every component has to finish its processes in a particular phase until it can proceed to the next. So, objection is a mechanism to allow a component to stall other components from proceeding to the next phase until it gets the chance to finish its own tasks. This is normally done using raise_objection() and drop_objection() methods from the uvm_phase class.
What is the difference between set_config_* and uvm_config_db ?
The basic set_config_* methods are mapped to corresponding uvm_config_db as :
Factory overrides can be done in four different ways:
Instance override by type of the component/object
Instance override by name of the component/object
Type override by type of the component/object
Name override by type of the component/object
How can we access a DUT signal in a component or sequence ?
Interface signals can be accessed via a virtual interface handle that points to the actual physical interface. Signals within the DUT can be accessed directly by providing a hierarchical RTL path to the signal such as top.eatable.fruits.apple.slice
What is RALGEN and how do you use it ?
RALGEN is a Synopsys tool to generate RAL model from an IPXACT specification file. You simply have to specify a few options and select the block for which you need to generate class structure for and provide them to the tool.
What are desired and mirrored values in RAL ?
Desired values are those that we want the design to have, and can later update the design with. Mirrored values are those that reflect the latest known values in the DUT.
What are reg2bus and bus2reg functions for ?
They are RAL functions that enable conversion from generic register contents to actual bus transactions and vice-versa. You have to define them based on the protocol you are dealing with by assigning the data object of the protocol with values from rw internal variable and vice-versa.
How would you debug a config db name or path mismatch problem ?
You can use the command-line define +UVM_CONFIG_DB_TRACE to dump information related to all SET and GET calls done on the configuration DB. It also shows you the path, and instance that makes the call.
What are the different TB components in UVM ?
Some of the major components are driver, monitor, scoreboard, sequencer, agent, environment, test and sequences.
Which phase takes more time and why ?
Run time phases take more time because they are the major phases that consume simulation time. The times taken for each test can be different because they all test different aspects of a design.
How do you connect a monitor with a scoreboard ?
You can declare the implementation of an analysis port within a scoreboard and connect the monitor's analysis port with it in the environment's connect method.
How do you connect driver and sequencer ?
Driver has a TLM port called seq_item_port that can be connected with the sequencer's seq_item_export in an agent's connect method.
What is uvm_config_db and uvm_resource_db ?
Both are mechanisms that allow a component to place an object in a central look-up table under a specified name and path, so that they can be retrieved by another component using the same name and path. The uvm_config_db class provides a convenience interface on top of the uvm_resource_db to simplify the basic interface that is used for configuring uvm_component instances.
What does a sequence normally contain ?
A sequence has a task called body() within which we can write the actual stimulus to test the design for a particular feature.
Write pseudo code for implementing an AHB-Lite driver.
The main point in writing an AHB driver is to realize that its a pipelined protocol and hence address phase of the next transaction should be active when the data phase of current transaction is on going. This is done by starting the same task twice in a fork join.
class ahb_driver extends uvm_driver;
virtual task run_phase (uvm_phase phase);
virtual task drive_tx();
// 1. Get hold of a semaphore
// 2. Get transaction packet from sequencer
// 3. Drive the address phase
// 4. Release semaphore
// 5. Drive data phase