Expression coverage is a type of code coverage that measures the percentage of Boolean expressions executed during the simulation. Here's an example of expression coverage RTL code:
module voting_circuit(input [7:0] in1, input [7:0] in2, input [7:0] in3, output reg [7:0] out); always @(in1, in2, in3) begin if((in1 > in2) && (in1 > in3)) begin out <= in1; end else if((in2 > in1) && (in2 > in3)) begin out <= in2; end else begin out <= in3; end end endmodule
In this example, the voting_circuit module takes in three input values and selects the largest one to output using a simple logic. The Boolean expressions include the comparison of in1 to in2 and in3, the comparison of in2 to in1 and in3, and the "or" condition in the final else statement.
To determine expression coverage, a testbench would need to be created that stimulates each Boolean expression in the module.
Here's an example of a SystemVerilog testbench that could be used to achieve expression coverage:
module voting_circuit_tb(); reg [7:0] in1; reg [7:0] in2; reg [7:0] in3; wire [7:0] out; voting_circuit dut(in1, in2, in3, out); initial begin in1 = 8'h05; in2 = 8'h08; in3 = 8'h10; #10; in1 = 8'h12; in2 = 8'h07; in3 = 8'h04; #10; in1 = 8'h01; in2 = 8'h01; in3 = 8'h20; #10; $finish; end endmodule
In this testbench, the input signals are stimulated with different values in each iteration. The
initial values cause in3 to be selected as the largest input. The second set of values causes in1 to be selected, and the final set causes in3 to be selected again through the use of two equal input values. This testbench would achieve 100% expression coverage for the voting_circuit module.