UVM has a lot of macros to allow the user to specify intent without the need to specify multiple types of SystemVerilog constructs.

Report Macros

This set of macros provide wrappers around the uvm_report_* reporting functions and primarily serve two purposes:

  • A check is made against the report's verbosity setting and the action for the id/severity pair before any string formatting is performed.
  • `__FILE__ and `__LINE__ information is automatically provided to the uvm_report_* call, which can be disabled by +define+UVM_REPORT_DISABLE_FILE_LINE as compilation argument.
Its worthwhile to note that these macros enforce a verbosity setting of UVM_NONE for warnings, errors and fatals so that you do not turn them off by mistake by setting the verbosity level too low.

/* Previous calls to uvm_report_* */
uvm_report_info("MYINFO1", $sformatf("val: %0d", val), UVM_LOW);
uvm_report_warning("MYWARN1", "This is a warning");
uvm_report_error("MYERR", "This is an error");
uvm_report_fatal("MYFATAL", "A fatal error has occurred");
/* New calls to `uvm_* */
`uvm_info("MYINFO1", $sformatf("val: %0d", val), UVM_LOW)
`uvm_warning("MYWARN1", "This is a warning")
`uvm_error("MYERR", "This is an error")
`uvm_fatal("MYFATAL", "A fatal error has occurred")

Utility Macros

The utils macros define the infrastructure needed to enable the object/component for correct factory operation. A utils macro should be used inside every user-defined class that extends uvm_object directly or in-directly, including uvm_sequence_item and uvm_component. Here's an example :

/* Example for user-defined object */
class mydata extends uvm_object;
  `uvm_object_utils (mydata)
  function new (string name = "mydata_inst");
    super.new (name);
/* Example for user-defined component */
class mycomponent extends uvm_component;
  `uvm_component_utils (mycomponent)
  function new (string name, uvm_component parent = null);
    super.new (name, parent);

Read more in Using factory overrides.

Sequence-Related Macros

These macros are used to start sequences and sequence items on the default sequencer m_sequencer. This is determined in a number of ways :

  • the sequencer handle provided in the uvm_sequence_base::start method
  • the sequencer used by the parent sequence
  • the sequencer that was set using the uvm_sequence_item::set_sequencer method

// Sequence Action Macros
// Sequence on Sequencer Action Macros
// Sequence Action Macros for Pre-Existing Sequences
// Sequencer Subtypes

Read more in How to execute sequences via `uvm_do macros ? and follow the set of links under Sequences in the sidebar to the left.

TLM Macros

These are implementation declaration macros that help to provide multiple implementation tasks for the same port interface as discussed in Using _decl macro in TLM. For example, compA implements the put() function for which it needs to have a port defined as put_imp.

class compA extends uvm_component;
  uvm_put_imp #(my_data, compA) put_imp;
  virtual task put (my_data t);
    // Implementation of the put

If compA is required to execute different put() implementations, then you need to create more than one put_imp port.

`uvm_put_imp_decl (_1)
`uvm_put_imp_decl (_2)
class compA extends uvm_component;
  uvm_put_imp_1 #(my_data, compA) put_imp1;
  uvm_put_imp_2 #(my_data, compA) put_imp2;
  function void put_1 (my_data t);
    // implementation for whats connected with put_imp1
  function void put_2 (my_data t);
    // implementation for whats connected with put_imp2

Shown below is the details of how this macro is implemented in UVM. You can see that it essentially creates two separate classes with the specified suffix SFX for this purpose and hence have separate put() implementation tasks.

`define uvm_put_imp_decl(SFX) \
class uvm_put_imp``SFX #(type T=int, type IMP=int) \
  extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \
  `UVM_IMP_COMMON(`UVM_TLM_PUT_MASK,`"uvm_put_imp``SFX`",IMP) \

Refer Using _decl macro in TLM for a real example. In a similar way you can use one of the following macros to create other port interfaces if required.


Register Define Macros

Macro Definition
`UVM_REG_ADDR_WIDTH Maximum address width in bits with a default value of 64
`UVM_REG_DATA_WIDTH Maximum data width in bits with a default value of 64
`UVM_REG_BYTENABLE_WIDTH Maximum number of byte enable bits with a default value of 1 per byte
`UVM_REG_CVR_WIDTH Maximum number of bits in a uvm_reg_cvr_t coverage model set

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