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Hardware behavior is made more configurable through control registers, and the verification of these registers has become one of the primary items in the to-do list of any design. It is quite pointless to test any other feature of a design if we cannot access/modify its register bits to change any of its functionality. Registers are typically accessed using low-bandwidth bus protocols like AMBA Advanced Peripehral Bus, IBM On-Chip Peripheral Bus or something similar developed in-house by a semiconductor firm. It's because of these registers that software can exercise greater control on the overall behavior of the chip, and most design specifications have a number of pages detailing the functionalities of each bit of every register.


Walking 1

A walking 1 is a test pattern that will perform a register write with 0x1 shifted to the left on each write. Let's take a 8-bit register and see how you can perform a walking 1 on it.

0 0 0 0  0 0 0 1
0 0 0 0  0 0 1 0
0 0 0 0  0 1 0 0
0 0 0 0  1 0 0 0
0 0 0 1  0 0 0 0
0 0 1 0  0 0 0 0
0 1 0 0  0 0 0 0
1 0 0 0  0 0 0 0

Doing a walking 1 pattern will help verify

  • No bit in RTL is stuck at 0
  • All the 8 bits are present in RTL
  • Only RW/WO bits are being written

Walking 0

A walking 0 is a test pattern that will perform a register write with all bits except LSB set to 1, and the O is shifted towards MSB. Let's take a 8-bit register and see how to perform a walking 0 on it

1 1 1 1  1 1 1 0
1 1 1 1  1 1 0 1
1 1 1 1  1 0 1 1
1 1 1 1  0 1 1 1 
1 1 1 0  1 1 1 1
1 1 0 1  1 1 1 1
1 0 1 1  1 1 1 1
0 1 1 1  1 1 1 1

Performing a walking 0 pattern will help verify

  • No bit in RTL is stuck at 1
  • All the 8 bits are present in RTL
  • Only RW/WO bits are being written

You have to be careful when validating the walking 1/0 pattern because, you are writing valid values to the register and there are chances that the design will react to these inputs and perform some transactions, and update the registers with some other value. For example, if there's a register bit 'ENBL' [bit position 2] that enables the design block, starts fetching data from its internal buffers and updates the DONE flag [bit position 9] in the same register. When the walking one pattern reaches 0x0000_0004, it will enable the module and by the time you read back the register, the design must have already finished its task of fetching data from internal buffers and might have set 'DONE' to 1. So, you get back 0x0000_0204.


Endian Check

Endianness is a convention used to interpret the ordering of data bytes when stored in memory. Big-Endian systems store the most significant byte in the smallest address, and the least significant byte in the largest address. Little-endian systems are just the opposite - MSB in largest address, LSB in smallest address.Let's consider a 32-bit register and in order to do an endian check.



endian

  • Do a full register write (32-bits) with a unique pattern eg: 0x1234_5678. Then read every byte of the register back with 8-bit reads and check the result.
  • Invert the pattern and write each byte individually into every byte of the register. Read back the whole register, after every write and check the result.

Architecture Endianness Default
ARM Bi-Endian Little
Intel x86 Little -
Intel Itanium Bi-Endian -
IBM PowerPC Bi-Endian Big-Endian
Motorola 68K Big-Endian -
Java Virtual Machine Big-Endian -
MIPS Bi-Endian -
SUN SPARC Big-Endian -

Many of the common file formats and network protocols have different endianness. Image formats like .gif and .bmp are little-endian whereas .jpg is big-endian. Protocols like USB and PCI are little endian whereas TCP/IP is big-endian. So, you can see that mixed endian systems that can have multiple blocks with different endianness, will need to address the issues in code portability and sharing of data. Since different cores, peripherals, and memory share data between them, there is a possibility for endian-conflict. And, it becomes essential to write endian-neutral software or make it work with the opposite byte-ordering to support code-portability.


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