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This forum uses BBCode, and that means you'll get to utilize the toolbar to insert emoticons, styles and other embedded items in your post. How to Use : Click on button on the toolbar, and then you can enter text between the two tags [xyz] and [...
I am working on example project (edaplayground) https://www.edaplayground.com/x/2gC5 It is divided into two different files (DUT & testbench) testbench has several classes in one file When I compile two files, no problem exist However,...
How to generate a constraint for a signal_1 which low for 8 clk cycles then it is high after 8th clk and again signal_1 is low for 16 clk cycles and again High after 16th clk ?...
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Uvm phases does synchronization like all run phases are started parallel and if any of the component run phase completes first it stays in the same run phase and waits till all others complete then what is the use of raising and dropping objection....
How do we resolve NOA null object access error in SOC or IP level complex testbench where there are numerous objects will be created. one way of doing it below. if(obj==null) print("your obj is null") Are there any other ways in OVM/UVM t...
What is Verdi and why is it important to hardware? What are the technical and business impacts of using Verdi? https://www.synopsys.com/verification/debug/verdi.html...
Hi, I am new to Chipverify, i am writing a constraint where rand bit [24:0]a,b,c; // ( a != b != c ) but i wrote this way : class ABC; rand bit [24:0] a,b,c; constraint c_mode { foreach a[i],b[j],c[k] if ...
steps to follow for the verification plan....
hi guys, i want to print the data in a table like below : +------------+-------------------------+--------------------------+ | index | number | Description | +------------+-------------------------+--------...
Hi, can anyone explain how to inject error in uvm with a simple example...
how to print this string in systemverilog module tb; string str='10ns'; // NOTE : str value is in single type quotation initial begin $display("%s",str); end endmodule i am getting syntax error when tried to print ...
How can we write an assertion for the following condition - A signal X can either be low for one clock cycle or it can be low for 4 clock cycle....
How to disable monitor for a particular sequence?...
Hi, When reading with " Using factory overrides " and tried example with uvm-factory-overrides.zip, I'm confused by this piece of code: `ifdef DRV_STYLE1 // Substitute all instances of base_driver with driver2 s...
Hi, I'm learning examples with virtual-sequence. The environment has instantiated three agents, one for apb, one for wb and one for spi. There is a virtual sequencer to generates sequences to these three different agents. I'm interested in this ques...
Hi, I'm running example of virtual-sequencer.zip. I'm curious on examples of uvm_config_db with "default_sequence" and sequence.start, so I changed code "my_pkg.sv" from virtual-sequencer.zip as this: class base_test ext...
Hi I have a question about how to preload the processor memories from a UVM agent the iput files are hex files....
From the following link i understood how to use uvm_put_imp_decl. I tried the same in my Scoreboard. But how to call different write function of respective monitor ????? `uvm_put_imp_decl (_1) `uvm_put_imp_decl (_2) class my_put_imp ...
Canu explain why uvM driver is non virtual class...
what is re active agent in uvm and how do we implement?...


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