Discussions tagged uvm

What is Verdi and why is it important to hardware? What are the technical and business impacts of using Verdi? https://www.synopsys.com/verification/debug/verdi.html...
In uvm we use raise objection and drop objection ? What is the background process except triggering process ? 2.in case we raise phase raise and forget drop objection then what the process ?...
I have a RAL model of registers in my design. I want to read all the register in RAL model. Can any one explain with example?...
From the following link i understood how to use uvm_put_imp_decl. I tried the same in my Scoreboard. But how to call different write function of respective monitor ????? `uvm_put_imp_decl (_1) `uvm_put_imp_decl (_2) class my_put_imp ...
Suppose i have a long running test say it ran for 24 hours and it encountered a UVM error. There might some more errors after this error. I fixed the first error. Now commonly i have to run the test for 24 hours to look at further errors. Is there...
What is UVM callback and how it is used in an Verification TB?...
How does two fork-join will behave in a body() task of a sequence ?? Will they be working sequentially or in parallel?...
How can we configure a UVM Verification TB of an IP for example i3c to support Hot Join? How can we program to include a Slave after any transaction is done ?...
I am new for UVM . I have doubt in phases why connect phase is bottom to top approach, why can't top to bottom. I have clear idea about build phase is top to bottom approach because before child creation, the parent should be created. But I can't und...
Is there a tutorial on how to setup the environment for multiple files in modelsim. I mean I got the creating project, and adding a single file compiling it thing with the long command where you specify the path to UVM directory in the first video al...
What is the difference between `uvm_do and start_item() finish_item() methods ?...
What are the ways to pass an interface handle other than using uvm_config_db or uvm_resource_db ? I know one way is something like I have entered in :...
hi sir ,i m using vcs . i m not able run this code,this is the error which i am getting,so what should i do for solve this error. Error-[SV-LCM-PND] Package not defined tb_top.sv, 11 top, "test_pkg::" Package scope resolution failed. Token 'tes...
Getting an error like the following : $uvm_type_name(r,val); | ncsim: *E,MSSYSTF (/proj/uvm_factory.svp,46|22): User Defined system task or function ($uvm_type_name) registered during elaboration and used within the simulation has not been registe...
UVM_FATAL @ 486000: [email protected]@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq What should I look for ?...
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