Discussions tagged system verilog

How to generate a constraint for a signal_1 which low for 8 clk cycles then it is high after 8th clk and again signal_1 is low for 16 clk cycles and again High after 16th clk ?...
What is Verdi and why is it important to hardware? What are the technical and business impacts of using Verdi? https://www.synopsys.com/verification/debug/verdi.html...
hi guys, i want to print the data in a table like below : +------------+-------------------------+--------------------------+ | index | number | Description | +------------+-------------------------+--------...
how to print this string in systemverilog module tb; string str='10ns'; // NOTE : str value is in single type quotation initial begin $display("%s",str); end endmodule i am getting syntax error when tried to print ...
What is the exact difference between mailbox and queue?...
Suppose i have a long running test say it ran for 24 hours and it encountered a UVM error. There might some more errors after this error. I fixed the first error. Now commonly i have to run the test for 24 hours to look at further errors. Is there...
Can we assign a base class handle which is not created to a extended class handle which is created? Let say we have - class A; ............... endclass class B extends from A; ............ endclass program main; A my_a; B ...
How does two fork-join will behave in a body() task of a sequence ?? Will they be working sequentially or in parallel?...
I am new for UVM . I have doubt in phases why connect phase is bottom to top approach, why can't top to bottom. I have clear idea about build phase is top to bottom approach because before child creation, the parent should be created. But I can't und...
Hii all How can i declare Array to store Slave Address. Each Slave have Register Bank with Respective Register Number. Data is stored in those Register bank. To clear things up i am attaching a file in which you can see what i want in figure. ...
What are the ways to pass an interface handle other than using uvm_config_db or uvm_resource_db ? I know one way is something like I have entered in :...
I have a piece of verilog code + SV tech bench. I want to know the memory usage of different blocks . Does simulator like VCS has any option to check memory usage? I have tried profile , but did not help me. Can any one pls guide me on this topic....
Hi, I am a beginner in this field. I would like to know the best books in system verilog....
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