Discussions tagged verification

What is Verdi and why is it important to hardware? What are the technical and business impacts of using Verdi? https://www.synopsys.com/verification/debug/verdi.html...
How can we write an assertion for the following condition - A signal X can either be low for one clock cycle or it can be low for 4 clock cycle....
Suppose i have a long running test say it ran for 24 hours and it encountered a UVM error. There might some more errors after this error. I fixed the first error. Now commonly i have to run the test for 24 hours to look at further errors. Is there...
I have been reading in many places that there's a 70% bottleneck in design cycle due to verification. Do you all think it's a bit exaggerated ?...
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