1. Suresh varma
  2. SystemVerilog
  3. Monday, 13 July 2020
How to generate a constraint for a signal_1 which low for 8 clk cycles then it is high after 8th clk and again signal_1 is low for 16 clk cycles and again High after 16th clk ?
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From the protocol diagram, I don't think you need any constraints. The protocol says that S has to be pulled low, followed by clock start and the first 8 clocks has to be low followed by a data pattern.
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  2. SystemVerilog
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