1. mohammed imran
  2. UVM
  3. Thursday, 25 June 2020
Hi,

I am new to Chipverify,

i am writing a constraint where

rand bit [24:0]a,b,c;

// ( a != b != c )

but i wrote this way :


class ABC;
rand bit [24:0] a,b,c;

constraint c_mode { foreach a[i],b[j],c[k]

if (a[i] == 1)

b[j]&c[k] != 1;

else if(b[j] == 1)

a[i]&c[k] != 1;

else if (c[k] == 1)

b[j]&a[i] != 1;
}

endclass



but i am getting errors,

can any one help me regarding this constraints
Responses (2)
Accepted Answer Pending Moderation
Hi,
If your intention is to generate unique values for a,b,c you can try

constraint c_unique{
unique {a,b,c};
}
  1. more than a month ago
  2. UVM
  3. # 1
Accepted Answer Pending Moderation
a != b != c is not supported in SV, and can be split like:

constraint c_abc {
a != b;
b != c;
c != a;
}


You do not have to treat every bit of a variable as a separate value.
  1. more than a month ago
  2. UVM
  3. # 2
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